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Etude de la fiabilité porteurs chauds et des
performances des technologies CMOS 0.13 μm - 2nm

Abstract : This work concern the study of the 130nm CMOS technology degradation, submitted to high energy carriers injections, witch are generated under high electrical fields. Consequences of these degradation mechanisms are found in a significant temporal drift of the representative electric transistor parameters These variations are related on the charges trapping in the gate oxide and electronic states generation at Oxide-Silicon (SiO2-Si) interface. This study presents in a first part basis of MOS structure operation and influence of interface states and oxide charges presence. Effects due to length reduction, as well as characterization technics are presented. Thereafter we expose the experimental means which allow to highlight degradation mechanismes and localization distinction. These methods are current-voltage or charge pumping measurements, and were adapted in order to answer to ultra thin gate oxide specificities. These devices, as well as other samples, representative of older technologies (500nm-12nm), were submitted to static stresses. We thus could highlight the evolution of the worst case degradations, but also of the degradation mechanisms, and thus, of the type of induced defects. Finally we describe lifetime extrapolation methods, based on hot carrier currents expression. These models do not take into account direct tunnel currents imposed by the thinness oxides (2nm), which strongly play in PMOS aging. We propose a simple model which allow to separate hot carriers flow on the one hand, and “cold” carriers (injected in tunnel mode) on the other hand.
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https://tel.archives-ouvertes.fr/tel-00117263
Contributor : Thierry Di Gilio <>
Submitted on : Monday, January 29, 2007 - 5:07:05 PM
Last modification on : Thursday, March 15, 2018 - 4:56:03 PM
Long-term archiving on: : Tuesday, September 21, 2010 - 11:53:07 AM

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  • HAL Id : tel-00117263, version 2

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Thierry Di Gilio. Etude de la fiabilité porteurs chauds et des
performances des technologies CMOS 0.13 μm - 2nm. Micro et nanotechnologies/Microélectronique. Université de Provence - Aix-Marseille I, 2006. Français. ⟨tel-00117263v2⟩

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