Skip to Main content Skip to Navigation

Secure Hardware Accelerators for Post Quantum Cryptography

Timo Zijlstra 1
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Shor’s quantum algorithm can be used to efficiently solve the integer factorisation problem and the discrete logarithm in certain groups. The security of the most commonly used public key cryptographic protocols relies on the conjectured hardness of exactly these mathematical problems. Post quantum cryptography relies on mathematical problems that are computationally hard for quantum computers, such as Learning with Errors (LWE) and its variants RLWE and MLWE. In this thesis, we present and compare FPGA implementations using HLS of LWE, RLWE and MLWE based public-key encryption algorithms. We discuss various trade-offs between security, computation time and hardware cost. The implementations are parallelized in order to obtain maximal speed-up. We also discuss hardware security and propose countermeasures against side channel attacks. We consider countermeasures from the state of the art, such as masking, and propose improvements to these algorithms. Moreover, we propose new countermeasures based on redundant number representation and random shuffling of operations. All our countermeasures are implemented and evaluated on FPGA to compare their cost and performance.
Complete list of metadata

Cited literature [124 references]  Display  Hide  Download
Contributor : Arnaud Tisserand Connect in order to contact the contributor
Submitted on : Wednesday, September 30, 2020 - 6:14:34 AM
Last modification on : Monday, October 11, 2021 - 2:24:02 PM
Long-term archiving on: : Monday, January 4, 2021 - 8:45:06 AM


  • HAL Id : tel-02953277, version 1



Timo Zijlstra. Secure Hardware Accelerators for Post Quantum Cryptography. Cryptography and Security [cs.CR]. Université Bretagne Sud, 2020. English. ⟨tel-02953277v1⟩



Les métriques sont temporairement indisponibles