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Réalisation et caractérisation de transistors MOS à base de nanofils verticaux en silicium

Abstract : In order to further downscaling of the MOS transistors, the semiconductor industry has anticipated the limitations of miniaturization by the introduction of new materials and new architectures. The advent of triple gate structures (FinFET) allowed mastering the short channel effects and further miniaturization efforts (14 nm technology node in 2014). The ultimate case to the electrostatic control of the gate on the channel is given by a gate completely surrounding the device channel. For this purpose, Gate All Around (GAA) nanowire transistor is considered as the most suitable structure for technology nodes below 7 nm. In this thesis, a large scale process for the realization of miniaturized MOSFETs based on vertical silicon nanowires has been developed. Firstly, the vertical nanowires were made by a top down approach by the transfer by etching of hard mask made of Hydrogen silsesquioxane (HSQ) resist created at low voltage electron beam lithography. An original design strategy called "star" was developed to define perfectly circular nanowires. Si nanowires are obtained by plasma etching then thinned by sacrificial wet oxidation. This method allows obtaining vertical Si nanowires with perfectly anisotropic walls, a perfect reproducibility and a maximum yield. The implementation of the MOSFETs on the nanowire network was done by successive engineering of nanoscale thin films (conductive and dielectric). In this context, an innovative process for producing insulation layers in HSQ by controlled chemical etching showed excellent flatness associated with surface roughness of less than 2 nm. Finally, a method using conventional UV photolithography has been developed to achieve the nanometer gate length transistor. These devices have demonstrated excellent electrical performances with conduction currents superior than 600 µA/µm and excellent control of short channel effects (subthreshold slope of 95 mV/dec and DIBL of 25 mV/V) despite extreme miniaturization of the gate length (15 nm). Finally, we present a first proof of concept of a CMOS inverter based on vertical nanowires technology.
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Submitted on : Thursday, October 13, 2016 - 12:01:09 PM
Last modification on : Thursday, June 10, 2021 - 3:03:52 AM
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  • HAL Id : tel-01261513, version 3


Youssouf Guerfi. Réalisation et caractérisation de transistors MOS à base de nanofils verticaux en silicium. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 2015. Français. ⟨NNT : 2015TOU30253⟩. ⟨tel-01261513v3⟩



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