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Contribution à la conception de circuits intégrés sécurisés : l'alternative asynchrone

Abstract : This work is focused on the development of new design techniques for
protecting integrated circuits against power analysis attacks by
exploiting the properties of asynchronous logic. In fact, among non
intrusive attacks which exploit the hardware weaknesses of cryptographic devices for retrieving confidential information, the power analysis attacks are the most efficient and the easiest to implement. In this work the countermeasures developed are based on Quasi Delay Insensitive asynchronous logic (QDI) and focused on the protection of integrated circuits against power analysis attacks. The properties of the QDI asynchronous logic are particularly interesting for securing an implementation because it enables the designer to precisely control the current activity. The work was first concentrated on the evaluation of the resistance of asynchronous logic to DPA. The results obtained demonstrate the potentiality of the QDI properties to improving chips' security compared to synchronous logic, and enable us to identify some limits of this approach. We propose a formal analysis to evaluate the sensitivity of QDI asynchronous logic to power analysis and then present new countermeasures that exploit the QDI logic topology. These studies lead to the specification of a new design methodology for implementing secure asynchronous chips which will be integrated in the TAST framework, TIMA Asynchronous Synthesis Tools.
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Contributor : Lucie Torella <>
Submitted on : Wednesday, January 25, 2006 - 6:05:10 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Monday, September 20, 2010 - 2:08:50 PM


  • HAL Id : tel-00011457, version 2




Ghislain Bouesse. Contribution à la conception de circuits intégrés sécurisés : l'alternative asynchrone. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2005. Français. ⟨tel-00011457v2⟩



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