«. , Advances in semiconductor memories have been very impressive. Their density . . . is ever increasing . . . algorithms with a test time of . . . order O(n 2 ), where n is the number of bits in the memory chip, are no longer acceptable for testing current . . . multi-Mega-bit memory chips

, « La génération d'un programme de test efficace est une tâche fondamentale dévolue aujourd'hui au concepteur. Le choix des modèles de fautes (pannes) considérés et les stratégies de test mises en oeuvre influencent profondément la qualité du produit livré aux clients. Par ailleurs, la part du coût de développement correspondant à la préparation des tests est en forte augmentation

, 80 6.2 Modélisation et détection des pannes dans la mémoire CMA, p.85

, 3.2 Tests des pannes mono-cellule et des pannes inter-mots, Conversion des Tests March orientés bits à des tests March orientés mots . 86 6.3.1

, 90 6.4.1 Ensemble de DBs pour la détection des pannes uCFsts, Détection des pannes intra-mots dans les trames de configuration

, 96 6.5.2 Pannes rCFs concurrentielles ( crCFs), Tests des pannes de couplage intra-mots restreintes dans les trames de configuration

.. .. Discussion,

.. .. Conclusion,

, techniques de tolérance aux pannes des fpgas de technologie sram

. Cependant, les pannes transitoires (SEUs) qui apparaissent le long du cycle de test ne peuvent pas être détectées

, Technique de duplication et comparaison La technique de duplication et de comparaison assure la sécurité en ligne contre les pannes dans un FPAG-SRAM. Elle est couramment utilisée dans de nombreux systèmes

, Elle nécessite la duplication d'un module fonctionnel, un comparateur et un contrôleur. Les pannes permanentes sont détectées par le maintien de l'historique des résultats passés, vol.157

, Si un module dupliqué génère plusieurs sorties erronées, il doit être séparé du système puis remplacé, vol.157

, Technique de redondance modulaire multiple (NMR)

. Dans-cette-technique, N modules (où N est impair) exécutent la même fonction. Un circuit de vote majoritaire recueille leurs résultats et choisit la valeur majoritaire en tant que résultat final. Ainsi, les pannes qui apparaissent dans la minorité des modules seront masquées

, La technique NMR est généralement utilisée sous la version TMR pour limiter le coût matériel, vol.157

, Comparaison des différentes techniques de tolérance aux pannes

L. Tableau and B. , survole les méthodes et techniques de tolérance aux pannes des FPGA-SRAMs

. Bibliographie,

V. D. Agrawal and S. C. Seth, Tutorial test generation for VLSI chips, 1988.

M. Bushnell and V. D. , Essentials of electronic testing for digital, memory and mixedsignal VLSI circuits, vol.17, 2000.

S. Angelo, C. Metra, S. Pastore, A. Pogutz, and G. Sechi, « Fault-tolerant voting mechanism and recovery scheme for tmr fpga-based systems », in Defect and Fault Tolerance in VLSI Systems, IEEE International Symposium on, pp.233-240, 1998.

S. Angelo, C. Metra, and G. Sechi, « Transient and permanent fault diagnosis for fpgabased tmr systems, Defect and Fault Tolerance in VLSI Systems, 1999. DFT'99. International Symposium on, pp.330-338, 1999.

G. Mojoli, D. Salvi, M. Sami, G. Sechi, and R. Stefanelli, Kite : a behavioural approach to fault-tolerance in fpga-based systems », in Defect and Fault Tolerance in VLSI Systems, IEEE International Symposium on, pp.327-334, 1996.

P. Samudrala, J. Ramos, and S. Katkoori, « Selective triple modular redundancy (stmr) based single-event upset (seu) tolerant synthesis for fpgas, IEEE Transactions on, vol.51, issue.5, pp.2957-2969, 2004.

F. Kastensmidt, L. Sterpone, L. Carro, and M. Reorda, On the optimal design of triple modular redundancy logic for sram-based fpgas, Proceedings of the conference on Design, Automation and Test in Europe, vol.2, pp.1290-1295, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181306

J. Lee, Y. Hu, R. Majumdar, L. He, and M. Li, « Fault-tolerant resynthesis with dual-output luts, Proceedings of the 2010 Asia and South Pacific Design Automation Conference, pp.325-330, 2010.

X. Products-;-», « World's Highest Capacity FPGA -Now Shipping, 2011.

N. Campregher, P. Cheung, G. Constantinides, and M. Vasilko, Analysis of yield loss due to random photolithographic defects in the interconnect structure of fpgas, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pp.138-148, 2005.

A. Doumar and H. Ito, « Detecting, diagnosing, and tolerating faults in sram-based field programmable gate arrays : a survey », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.11, issue.3, pp.386-405, 2003.

J. A. Cheatham, J. M. Emmert, and S. Baumgart, « A survey of fault tolerant methodologies for fpgas, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.11, issue.2, pp.501-533, 2006.

A. Djupdal and P. Haddow, Yield enhancing defect tolerance techniques for fpgas, 2006.

W. House, Cyberspace policy review : Assuring a trusted and resilient information and communications infrastructure, vol.3, 2009.

K. Stouffer, J. Falco, and K. Scarfone, « Guide to industrial control systems (ics) security », NIST Special Publication, vol.800, p.82, 2007.

C. Of, H. Ronald, and H. James, Security requirements for cryptographic modules

G. Moore, « Progress in digital integrated ceci est un test electronics, Electron ceci est un test Devices Meeting, 1975 International, vol.21, pp.11-13, 1975.

S. Hauck and A. Dehon, Reconfigurable computing : the theory and practice of FPGA-based computation, Cité dans les pages 9, vol.11, p.12, 2010.

A. Greenfield, Everyware : The dawning age of ubiquitous computing. New Riders, 2010.

S. Pillement, Conception d'architectures reconfigurables dynamiquement : Du silicium au système, Université Rennes, vol.1, 2010.

T. J. Callahan, J. R. Hauser, and J. Wawrzynek, Computer, vol.33, issue.4, pp.62-69, 2000.

L. Bossuet, Exploration de l'espace de conception des architectures reconfigurables, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00089397

R. David, D. Chillet, S. Pillement, and O. Sentieys, Dart : a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints », Résumé, 2003.

M. I. Gordon, W. Thies, and S. Amarasinghe, « Exploiting coarse-grained task, data, and pipeline parallelism in stream programs, ACM SIGOPS Operating Systems Review, vol.40, pp.151-162, 2006.

R. Koch, T. Pionteck, C. Albrecht, and E. Maehle, Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, p.8, 2006.

J. M. Rabaey, Low-power silicon architecture for wireless communications : embedded tutorial, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, pp.377-380, 2000.

S. Derrien, Etude quantitative des techniques de partitionnement de réseaux de processeurs pour l'implantation sur circuits FPGA, Rennes, vol.1, 2002.

S. Kilts, Advanced FPGA design : architecture, implementation, and optimization, 2007.

U. Farooq, Z. Marrakchi, and H. Mehrez, « Tree-based asif using heterogeneous blocks, Tree-based Heterogeneous FPGA Architectures, vol.17, pp.153-171, 2012.

I. Kuon, R. Tessier, and J. Rose, Fpga architecture : Survey and challenges », Foundations and Trends in Electronic Design Automation, vol.2, pp.135-253, 2008.

D. K. Iakovidis, D. E. Maroulis, and D. G. Bariamis, « Fpga architecture for fast parallel computation of co-occurrence matrices, Microprocessors and Microsystems, vol.31, pp.160-165, 2007.

S. Trimberger, Field-programmable gate array technology, 1994.

J. Huang, M. B. Tahoori, and F. Lombardi, « Fault tolerance of switch blocks and switch block arrays in fpga, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.13, pp.794-807, 2005.

J. Huang, M. B. Tahoori, and F. Lombardi, Routability and fault tolerance of fpga interconnect architectures, pp.479-488, 2004.

. Xilinx, Virtex-5 FPGA Configuration User Guide », Xilinx User Guide (v5.3) UG190, vol.1, p.83, 2009.

. Xilinx, Datasheets Virtex-4, Virtex-5, Virtex-6, Virtex-7. UG070, UG190, UG360, UG470 », www.xilinx.com, 2014.

Y. Akasaka and T. Nishimura, « Concept and basic technologies for 3-d ic structure, Electron Devices Meeting, vol.32, pp.488-491, 1986.

P. Ramm, A. Klumpp, R. Merkel, J. Weber, R. Wieland et al., « 3d system integration technologies, MRS Proceedings, vol.766, pp.5-6, 2003.

, Decembre 16. Xilinx, UltraScale Architecture Configuration, vol.570, 2016.

A. Ullah, « Dependable system design for reconfigurable safety-critical applications, vol.17, 2015.

. Xilinx, Embedded Processor Block in Virtex-5 FPGAs », Xilinx User Guide (v5.3) UG200, vol.1, 2010.

«. Xilinx and . Development-system-reference-guide, Xilinx Development System Reference Guide (v10.1), vol.1, 2008.

M. Liu, W. Kuehn, Z. Lu, and A. Jantsch, « Run-time partial reconfiguration speed investigation and architectural design space exploration », Field Programmable Logic and Applications, pp.498-502, 2009.

, « Partial reconfiguration user guide », UG702 (v14. 5), 2013.

P. R. Guide, Ug702 (v12. 3), xilinx », Inc., October, vol.5, 2010.

K. B. Chehida, Méthodologie de partitionnement logiciel/matériel pour plateformes reconfigurables dynamiquement, 2004.

K. Vipin and S. A. Fahmy, « Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration, Reconfigurable Computing : Architectures, Tools and Applications, pp.13-25, 2012.

J. Note and É. Rannaud, From the bitstream to the netlist. », in FPGA, vol.8, pp.264-264, 2008.

C. Beckhoff, D. Koch, and J. Torresen, « Portable module relocation and bitstream compression for xilinx fpgas, Field Programmable Logic and Applications (FPL), pp.1-8, 2014.

E. Eto, « Difference-based partial reconfiguration, 2003.

D. Lardner and . Babbage, s calculating engine, Edinburgh Review, vol.59, issue.120, pp.263-327, 1834.

A. Avi?ienis, J. Laprie, and B. Randell, « Dependability and its threats : a taxonomy, Building the Information Society, pp.91-120, 2004.

M. Wirthlin, D. Lee, G. Swift, and H. Quinn, « A method and case study on identifying physically adjacent multiple-cell upsets using 28-nm, interleaved and secded-protected arrays, 2014.

J. Lach, W. Mangione-smith, and M. Potkonjak, « Low overhead fault-tolerant FPGA systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.6, issue.2, pp.212-221, 1998.

S. Drimer, « Total configuration memory cell validation built in self test (bist) circuit », août, vol.5, 2008.

J. M. Emmert, C. E. Stroud, and M. Abramovici, Online fault tolerance for fpga logic blocks », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, issue.2, pp.216-226, 2007.

I. Koren and Z. Koren, « Defect tolerance in vlsi circuits : techniques and yield analysis, Proceedings of the IEEE, vol.86, issue.9, pp.1819-1838, 1998.

A. Doumar and H. Ito, « Fault tolerance fpgas by shifting the configuration data, International Conference on Military and Aerospace Programmable Logic Devices, pp.377-384

J. Lach, W. H. Mangione-smith, and M. Potkonjak, « Algorithms for efficient runtime fault recovery on diverse fpga architectures, Defect and Fault Tolerance in VLSI Systems, 1999. DFT'99. International Symposium on, pp.386-394, 1999.

R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider et al., « Plasma : an fpga for million gate systems, Field-Programmable Gate Arrays, 1996. FPGA'96. Proceedings of the 1996 ACM Fourth International Symposium on, pp.10-16, 1996.

W. B. Culbertson, R. Amerson, R. J. Carter, P. Kuekes, and G. Snider, « Defect tolerance on the teramac custom computer, Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on, pp.116-123, 1997.

R. Leveugle, Test des circuits intégrés numériques : Conception orientée testabilité, vol.2, pp.2461-2462, 2002.

M. Dubois, Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA/DELTA, 2011.

S. Hamdioui and A. J. Van-de-goor, « An experimental analysis of spot defects in srams : realistic fault models and tests, Proceedings of the Ninth Asian, pp.131-138, 2000.

S. Hamdioui, Z. Al-ars, and A. J. , Van de Goor, « Testing static and dynamic faults in random access memories, Proceedings 20th IEEE, pp.395-400, 2002.

S. Hamdioui, G. Gaydadjiev, and A. J. , Van de Goor, « The state-of-art and future trends in testing embedded memories, Memory Technology, Design and Testing, pp.54-59, 2004.

S. Hamdioui, Testing static random access memories : defects, fault models and test patterns, vol.26, 2004.

A. Van-de-goor, Testing semiconductor memories : theory and practice, 1991.

C. Papameletis, B. Keller, V. Chickermane, S. Hamdioui, and E. J. Marinissen, « A dft architecture and tool flow for 3d-sics with test data compression

S. Hamdioui, Z. Al-ars, A. J. Van-de-goor, and M. Rodgers, « Dynamic faults in randomaccess-memories : Concept, fault models and tests, Journal of Electronic Testing, vol.19, issue.2, pp.195-205, 2003.

H. Kukner, S. Khan, P. Weckx, P. Raghavan, S. Hamdioui et al., « Comparison of reaction-diffusion and atomistic trap-based bti models for logic gates », Device and Materials Reliability, IEEE Transactions on, vol.14, issue.1, pp.182-193, 2014.

S. Dutt, V. Verma, and V. Suthar, Built-in-self-test of fpgas with provable diagnosabilities and high diagnostic coverage with application to online testing », Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.27, issue.2, pp.309-326, 2008.

V. Verma, S. Dutt, and V. Suthar, « Efficient on-line testing of fpgas with provable diagnosabilities, Proceedings of the 41st annual Design Automation Conference, pp.498-503, 2004.

S. Dutt, V. Shanmugavel, and S. Trimberger, « Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays, IEEE/ACM International Conference on, pp.173-176, 1999.

N. R. Mahapatra and S. Dutt, « Efficient network-flow based techniques for dynamic fault reconfiguration in fpgas, Digest of Papers. Twenty-Ninth Annual International Symposium on, pp.122-129, 1999.

M. Abramovici, C. Strond, C. Hamilton, S. Wijesuriya, and V. Verma, Using roving stars for on-line testing and diagnosis of fpgas in fault-tolerant applications, Test Conference, pp.973-982, 1999.

M. Abramovici, C. E. Stroud, and J. M. Emmert, Online bist and bist-based diagnosis of fpga logic blocks », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.12, issue.12, pp.1284-1294, 2004.

M. Abramovici, C. Stroud, B. Skaggs, and J. Emmert, « Improving on-line bist-based diagnosis for roving stars, Proceedings. 6th IEEE International, pp.31-39, 2000.

M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, « Testing the interconnect of ram-based fpgas, IEEE Design & Test of Computers, issue.1, pp.45-50, 1998.

A. Doumar, S. Kaneko, and H. Ito, Defect and fault tolerance fpgas by shifting the configuration data, Defect and Fault Tolerance in VLSI Systems, 1999. DFT'99. International Symposium on, pp.377-385, 1999.

W. K. Huang, F. J. Meyer, X. Chen, and F. Lombardi, « Testing configurable lut-based fpga's », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.6, issue.2, pp.276-283, 1998.

K. A. Kwiat, « Dynamically reconfigurable fpga apparatus and method for multiprocessing and fault tolerance », août 3 1999. US Patent 5,931,959

K. Kwiat and S. Hariri, « Efficient hardware fault tolerance using field-programmable gate arrays, Proceedings ISSAT International Conference on Reliability and Quality in Design, pp.59-64, 1995.

A. Sudarsanam, R. Kallam, and A. Dasu, « Prr-prr dynamic relocation, Computer Architecture Letters, vol.8, issue.2, pp.44-47, 2009.

A. Sreeramareddy, J. G. Josiah, A. Akoglu, A. Stoica, and . Scars, Scalable self-configurable architecture for reusable space systems, Adaptive Hardware and Systems, 2008. AHS'08. NASA/ESA Conference on, pp.204-210, 2008.

A. Sudarsanam, R. Barnes, J. Carver, R. Kallam, and A. Dasu, « Dynamically reconfigurable systolic array accelerators : A case study with extended kalman filter and discrete wavelet transform algorithms, IET computers & digital techniques, vol.4, issue.2, pp.126-142, 2010.

S. Corbetta, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto et al., « Internal and external bitstream relocation for partial dynamic reconfiguration », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.17, issue.11, pp.1650-1654, 2009.

J. Heiner, B. Sellers, M. Wirthlin, and J. Kalb, « Fpga partial reconfiguration via configuration scrubbing, Field Programmable Logic and Applications, pp.99-104, 2009.

M. Straka, J. Kastil, and Z. Kotasek, « Fault tolerant structure for sram-based fpga via partial dynamic reconfiguration, Digital System Design : Architectures, Methods and Tools (DSD), pp.365-372, 2010.

H. Tan and R. F. Demara, « A physical resource management approach to minimizing fpga partial reconfiguration overhead, Reconfigurable Computing and FPGA's, pp.1-5, 2006.

H. Tan and R. F. Demara, « A multilayer framework supporting autonomous run-time partial reconfiguration », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.16, issue.5, pp.504-516, 2008.

W. R. Moore, A review of fault-tolerant techniques for the enhancement of integrated circuit yield, Proceedings of the IEEE, vol.74, pp.684-698, 1986.

K. Morgan, D. Mcmurtrey, B. Pratt, and M. Wirthlin, « A comparison of tmr with alternative fault-tolerant design techniques for fpgas, IEEE Transactions on, vol.54, issue.6, pp.2065-2072, 2007.

N. J. Howard, A. M. Tyrrell, and N. M. Allinson, « The yield enhancement of fieldprogrammable gate arrays », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.2, issue.1, pp.115-123, 1994.

F. Hanchek and S. Dutt, « Node-covering based defect and fault tolerance methods for increased yield in fpgas, Ninth International Conference on, pp.225-229, 1996.

M. Taouil, S. Hamdioui, K. Beenakker, and E. Marinissen, « Test impact on the overall dieto-wafer 3d stacked ic cost, Journal of Electronic Testing, pp.1-11, 2011.

X. Products, Virtex-5 FPGA user guide -Now Shipping, 2010.

M. Giraud, Sûreté de fonctionnement des systèmes : Principes et définitions », Techniques de l'ingénieur. Electronique, vol.5, 2005.

A. Avi?ienis, J. Laprie, and B. Randell, Dependability and its threats : a taxonomy », Building the Information Society, vol.57, pp.91-120, 2004.

F. Kastensmidt, L. Carro, R. Da, and L. Reis, Fault-tolerance Techniques for SRAM-based FPGAs, vol.32, 2006.

S. Bonacini, F. Faccio, K. Kloukinas, and A. Marchioro, « An seu-robust configurable logic block for the implementation of a radiation-tolerant fpga », Nuclear Science, IEEE Transactions on, vol.53, issue.6, pp.3408-3416, 2006.

R. Lyons and W. Vanderkulk, « The use of triple-modular redundancy to improve computer reliability, IBM Journal of Research and Development, vol.6, issue.2, pp.200-209, 1962.

M. Berg, H. Kim, M. Friendlich, C. Perez, C. Seidleck et al., « Seu analysis of complex circuits implemented in actel rtax-s fpga devices », Nuclear Science, IEEE Transactions on, issue.99, pp.1-1, 2011.

G. Foucard, Taux dérreurs dues aux radiations pour des applications implémentées dans des FPGAs à base de mémoire SRAM : prédiction versus mesures, 2010.

H. Asadi, M. B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, « Soft error susceptibility analysis of sram-based fpgas in high-performance information systems, IEEE Transactions on Nuclear Science, vol.54, issue.6, pp.2714-2726, 2007.

E. Normand, « Correlation of inflight neutron dosimeter and seu measurements with atmospheric neutron model », Nuclear Science, IEEE Transactions on, vol.48, issue.6, 1996.

, rtax-s/sl radtolerant fpgas, 2007.

M. and B. Jirad, Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes, 2013.

F. G. De-lima, R. A. Da, and L. Reis, « Designing single event upset mitigation techniques for large sram-based fpga devices, 2001.

X. She and S. Trimberger, « Scheme to minimise short effects of single-event upsets in triplemodular redundancy, IET computers & digital techniques, vol.4, issue.1, pp.50-55, 2010.

H. Quinn, G. Allen, G. Swift, C. Tseng, P. Graham et al., Seususceptibility of logical constants in xilinx fpga designs », Nuclear Science, vol.56, pp.3527-3533, 2009.

M. Berg, C. Poivey, D. Petrick, D. Espinosa, A. Lesea et al., « Effectiveness of internal versus external seu scrubbing mitigation strategies in a xilinx fpga : Design, test, and analysis », Nuclear Science, IEEE Transactions on, vol.55, issue.4, pp.2259-2266, 2008.

B. Bridgford, C. Carmichael, and C. W. Tseng, Single-event upset mitigation selection guide », Xilinx Application Note, XAPP987 (v1. 0), 2008.

C. Carmichael and C. Tseng, « Correcting single-event upsets in virtex-4 fpga configuration memory », Xilinx Application Note (XAPP197), 2009.

A. Tiwari and K. Tomko, Enhanced reliability of finite-state machines in fpga through efficient fault detection and correction », Reliability, IEEE Transactions on, vol.54, issue.3, pp.459-467, 2005.

J. and V. Neumann, Probabilistic logics and the synthesis of reliable organisms from unreliable components », Automata studies, vol.34, pp.43-98, 1956.

R. Oliveira, A. Jagirdar, and T. Chakraborty, « A tmr scheme for seu mitigation in scan flipflops, Quality Electronic Design, 2007. ISQED'07. 8th International Symposium on, pp.905-910, 2007.

C. Stroud, « Reliability of majority voting based vlsi fault-tolerant circuits », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.2, issue.4, pp.516-521, 1994.

M. Radu, D. Pitica, and C. Posteuca, Reliability and failure analysis of voting circuits in hardware redundant design, Electronic Materials and Packaging, pp.421-423, 2000.

C. Bolchini, A. Miele, and M. Santambrogio, Tmr and partial dynamic reconfiguration to mitigate seu faults in fpgas », in Defect and Fault-Tolerance in VLSI Systems, DFT'07. 22nd IEEE International Symposium on, pp.87-95, 2007.

S. Trimberger, Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices, US Patent, vol.6, issue.2, p.731, 2004.

Z. Huang and H. Liang, « A new radiation hardened by design latch for ultra-deep-sub-micron technologies, On-Line Testing Symposium, pp.175-176, 2008.

M. Fazeli, A. Patooghy, S. Miremadi, and A. Ejlali, « Feedback redundancy : a power efficient seu-tolerant latch design for deep sub-micron technologies, Dependable Systems and Networks, 2007. DSN'07. 37th Annual IEEE/IFIP International Conference on, pp.276-285, 2007.

L. Wang, S. Yue, and Y. Zhao, « Low-overhead seu-tolerant latches, Microwave and Millimeter Wave Technology, 2007. ICMMT'07. International Conference on, pp.1-4, 2007.

M. Nicolaidis, R. Perez, and D. Alexandrescu, « Low-cost highly-robust hardened cells using blocking feedback transistors, VLSI Test Symposium, pp.371-376, 2008.

O. Amusan, A. Steinberg, A. Witulski, B. Bhuva, J. Black et al., Single event upsets in a 130 nm hardened latch design due to charge sharing, Reliability physics symposium, 2007. proceedings. 45th annual. ieee international, pp.306-311, 2007.

T. Calin, M. Nicolaidis, and R. Velazco, « Upset hardened memory design for submicron cmos technology », Nuclear Science, IEEE Transactions on, vol.43, issue.6, pp.2874-2878, 1996.

Y. Shiyanovskii, F. Wolff, and C. Papachristou, « Sram cell design protected from seu upsets, On-Line Testing Symposium, pp.169-170, 2008.

R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, and R. Koga, « Two cmos memory cells suitable for the design of seu-tolerant vlsi circuits », Nuclear Science, IEEE Transactions on, vol.41, issue.6, pp.2229-2234, 1994.

H. Zarandi, S. Miremadi, C. Argyrides, and D. Pradhan, « Fast seu detection and correction in lut configuration bits of sram-based fpgas, Parallel and Distributed Processing Symposium, pp.1-6, 2007.

A. Dutta and N. Touba, Multiple bit upset tolerant memory using a selective cycle avoidance based sec-ded-daec code, VLSI Test Symposium, pp.349-354, 2007.

A. Dutta and N. Touba, « Reliable network-on-chip using a low cost unequal error protection code », in Defect and Fault-Tolerance in VLSI Systems, DFT'07. 22nd IEEE International Symposium on, pp.3-11, 2007.

J. Singh, J. Mathew, M. Hosseinabady, and D. Pradhan, « Single event upset detection and correction », in Information Technology, 10th International Conference on, pp.13-18, 2007.

R. Le, Soft error mitigation using prioritized essential bits, Xilinx XAPP538 (v1. 0), 2012.

K. Chapman, « Virtex-5 seu critical bit information extending the capability of the virtex-5 seu controller, Xilinx Documentation SEU lounge, 2010.

U. Legat, A. Biasizzo, and F. Novak, Seu recovery mechanism for sram-based fpgas, IEEE Transactions on Nuclear Science, vol.59, issue.5, pp.2562-2571, 2012.

A. Van-de-goor and I. Tlili, « A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories », Computers, IEEE Transactions on, vol.52, issue.10, p.103, 2003.

S. Hamdioui and A. Van-de-goor, « Efficient tests for realistic faults in dual-port srams, IEEE Transactions on Computers, pp.460-473, 2002.

S. Hamdioui, Z. Al-ars, A. Van-de-goor, and M. Rodgers, « Linked faults in random access memories : concept, fault models, test algorithms, and industrial results », Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.23, issue.5, pp.737-757, 2004.

Z. Al-ars and S. Hamdioui, « Fault diagnosis using test primitives in random access memories, 2009 Asian Test Symposium, pp.403-408, 2009.

D. Gaitonde and D. Walker, Circuit-level modeling of spot defects », in Defect and Fault Tolerance on VLSI Systems, IEEE, pp.63-66, 1991.

J. Knaizuk and C. Hartmann, « An optimal algorithm for testing stuck-at faults in random access memories », Computers, IEEE Transactions on, vol.100, issue.11, pp.1141-1144, 1977.

, Virtex-5 FPGA Configuration User Guide, vol.191, 2009.

R. Dekker, F. Beenker, and L. Thijssen, « A realistic fault model and test algorithms for static random access memories », Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.9, issue.6, pp.567-572, 1990.

M. Marinescu, Simple and efficient algorithms for functional ram testing, Proc. Int. Test Conf, pp.236-239, 1982.

A. Van-de-goor and I. Tlili, « March tests for word-oriented memories, Design, Automation and Test in Europe, pp.501-508, 1998.

M. Nicolaidis, V. Castro-alves, and H. Bederr, « Testing complex couplings in multiport memories », Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.3, issue.1, pp.59-71, 1995.

, Embedded Processor Block in Virtes-5 FPGAs, vol.200, 2010.

R. Treuer and V. Agarwal, « Fault location algorithms for repairable embedded rams, Test Conference, pp.825-834, 1993.

F. Lahrach, A. Abdaoui, A. Doumar, and E. Chatelet, « A novel sram-based fpga architecture for defect and fault tolerance of configurable logic blocks, Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.305-308, 2010.

F. Lahrach, A. Doumar, E. Châtelet, and A. Abdaoui, « Master-slave tmr inspired technique for fault tolerance of sram-based fpga, VLSI (ISVLSI), pp.58-62, 2010.

F. Lahrach, A. Doumar, and E. Chatelet, « Fault tolerance of sram-based fpga via configuration frames, Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.139-142, 2011.

F. Lahrach, A. Doumar, and E. Chatelet, « Fault tolerance of multiple logic faults in srambased fpga systems, Digital System Design (DSD), pp.231-238, 2011.

G. Sébastien, Modélisation et contrôle formel de la reconfiguration application aux systèmes embarqués dynamiquement reconfigurables, 2012.

R. David, Architecture reconfigurable dynamiquement pour applications mobiles, Rennes, vol.1, 2003.

M. Herbordt, T. Vancourt, Y. Gu, B. Sukhwani, A. Conti et al., « Achieving high performance with fpga-based computing, Computer, vol.40, issue.3, pp.50-57, 2007.

E. Stott, P. Sedcole, and P. Y. Cheung, « Fault tolerant methods for reliability in fpgas, Field Programmable Logic and Applications, pp.415-420, 2008.

E. Stott, J. Wong, P. Sedcole, and P. Cheung, « Degradation in fpgas : measurement and modelling, Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, pp.229-238, 2010.

N. Goel and K. Paul, « Hardware controlled and software independent fault tolerant fpga architecture, ADCOM 2007. International Conference on, pp.497-502, 2007.

J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici, « Dynamic fault tolerance in fpgas via partial reconfiguration, Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on, pp.165-174, 2000.

A. Jacobs, A. George, and G. Cieslewski, « Reconfigurable fault tolerance : A framework for environmentally adaptive fault mitigation in space, Field Programmable Logic and Applications, pp.199-204, 2009.

B. Dave, N. Jha, and . Cofta, Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance », Computers, IEEE Transactions on, vol.48, issue.4, pp.417-441, 1999.

Y. Xie, W. Wolf, and . Asicosyn, Co-synthesis of conditional task graphs with custom asics, Proceedings. 4th International Conference on, pp.130-135, 2001.

B. Pratt, M. Caffrey, P. Graham, K. Morgan, and M. Wirthlin, « Improving fpga design robustness with partial tmr, Reliability Physics Symposium Proceedings, pp.226-232, 2006.

W. Huang, S. Mitra, and E. Mccluskey, « Fast run-time fault location in dependable fpgabased applications », in Defect and Fault Tolerance in VLSI Systems, Proceedings. 2001 IEEE International Symposium on, pp.206-214, 2001.

A. El-attar and G. Fahmy, « A study of fault coverage of standard and windowed watchdog timers, Signal Processing and Communications, 2007. ICSPC 2007. IEEE International Conference on, pp.325-328, 2007.

, Publications Ce mémoire reprend des concepts, des idées et des supports utilisés précédemment dans les publications suivantes : Conférences internationales

F. Lahrach, A. Doumar, and E. Châtelet, Fault Tolerance of Multiple Logic Faults in SRAM-based FPGA Systèmes, Euromicro Conference on Digital System Design (DSD), pp.231-238, 2011.

F. Lahrach, A. Doumar, and E. Châtelet, Fault Tolerance of SRAMbased FPGA via Configuration Frames " in Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE 14th International Symposium on. IEEE, pp.139-142, 2011.

F. Lahrach, A. Doumar, E. Châtelet, and A. Abdaoui, Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA, Proceedings of the 2010 IEEE Annual Symposium on VLSI, pp.58-62, 2010.
URL : https://hal.archives-ouvertes.fr/hal-02269699

F. Lahrach, A. Abdaoui, A. Doumar, and E. Châtelet, A Novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks, Design and Diagnostics of Electronic Circuits and Systems (DDECS), Avril 2010 IEEE 13th International Symposium on, pp.305-308, 2010.
URL : https://hal.archives-ouvertes.fr/hal-02563086

, 32 heures de TP (48 UTP) -Bases de la physique pour l'ingénieur (PHYS 01) : 36 heures de TP (54 UTP) -Mesure physique et instrumentation (MS11) : 30 heures de TP (45 UTP) -Bases de l'informatique (LO 01) : 26 heures de TP (39 UTP) -Circuits de l'électronique analogique (EN01) : 93 heures de TD (139.5 UTP) -Outils mathématiques pour l'ingénieur, Circuits de l'électronique analogique, 2009.

E. École-supérieure-d'ingénieurs-léonard-de-vinci, Circuits de l'électronique analogique, pp.2014-2016