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Theses

Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM

Abstract : Nowadays, SRAM-based FPGAs are omnipresent for embedded electronic applications. Consequently, these circuits became the key player of the overall System-On-Chip (SoC) yield enhancement. However, faults are increasingly pronounced in these emergent technologies, from permanent faults arising from circuit processing at nanometer scales to transient soft errors arising from high-energy particle hits. So fault-tolerance of SRAM-based FPGA is an important system metric to ensure the dependability of embedded applications. The first part of this thesis exposes a comprehensive technique to cope with multiple faults in applications implemented in SRAM-based FPGA without incurring substantial area, power, or performance penalties. This approach has three main benefits compared to redundancy-based fault-tolerance: it’s very low overhead, the option for runtime management, and its complete flexibility. Run-time management can be a very valuable feature of a system, particularly for mission-critical applications. This fault-tolerance approach handles runtime problems on-line, minimizing the amount of system downtime and eliminating the need for outside intervention. The last part of this thesis is oriented toward configuration memory array of SRAM-based FPGA test and diagnostic. New fault models in configuration frames and March algorithms are proposed. These tests have the advantage to benefit from a fast implementation and achieving high fault coverage
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Farid Lahrach. Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM. Systèmes embarqués. Université de Technologie de Troyes, 2016. Français. ⟨NNT : 2016TROY0028⟩. ⟨tel-02953029⟩

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