, system_monitor: recvTimingReq: src system.physmem.cpu_side_ccn.slave[2] ReadUniqueReq expr 0 0x401480 111: system.physmem.cpu_side_ccn.system_monitor: copying for ccn pkt to global pkt: pkt ReadUniqueReq reqList ReadUniqueReq state 4 112: system.physmem, cpu_side_ccn.snoop_filter: recvTimingReq: src system.physmem.cpu_side_ccn.slave[2] ReadUniqueReq 0x401480 SF size: 0 lat: 1 112: system.physmem.cpu_side_ccn.snoop_filter: lookupRequest: SF value 0.1 112: system.physmem.cpu_side_ccn.snoop_filter: lookupRequest: new SF value 1.1 112: system.physmem.cpu_side_ccn.snoop_filter: Resp : forwardTiming for ReadUniqueReq address 401480 size 64 114: system.physmem.cache0: recvTimingSnoopReq for ReadUniqueReq address 401480 size 64 114: system.physmem.cache0: handleSnoop for ReadUniqueReq address 401480 size 64 114: system.physmem.cache0: Block for addr 401480 being updated in Cache 114: system.physmem.cache0: Block addr 401480 (ns) moving from state 7
, En effet, la démarche de co-design n'est pas une activité isolée de la conception de l'ensemble d'un système. Un des problèmes qui pourrait être étudié est le problème du partitionnement matériel/logiciel qui
, Ce dernier est un problème NP-complet et nécessite de mettre en oeuvre des méthodes d'optimisation combinatoires avancées pour résoudre efficacement le problème, ARM website, pp.2015-2016, 2015.
, GEM5 website, 2015.
, ARM website, pp.2016-2025, 2016.
, BULL website, 2016.
An evaluation of directory schemes for cache coherence, In ACM SIGARCH Computer Architecture News, vol.16, pp.280-298, 1988. ,
The uniform memory hierarchy model of computation, Algorithmica, vol.12, issue.2-3, pp.72-109, 1994. ,
, AMBA and Specification-AXI, 2011.
, , p.22
Cache coherence protocols : Evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), vol.4, issue.4, pp.273-298, 1986. ,
Symmetric multiprocessing computer with non-uniform memory access architecture, US Patent, vol.5, p.146, 1999. ,
On the formal specification and verification of cim architectures using lotos, Computers in Industry, vol.7, issue.6, pp.491-504, 1986. ,
Network-oriented full-system simulation using m5, Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), pp.36-43, 2003. ,
A new solution to coherence problems in multicache systems, IEEE Transactions on Computers, vol.100, issue.12, pp.1112-1118, 1978. ,
Multiprocessor features of the hp corporate business servers, Compcon Spring'93, pp.330-337, 1993. ,
Model checking, 1999. ,
Formal methods : State of the art and future directions, ACM Computing Surveys (CSUR), vol.28, issue.4, pp.626-643, 1996. ,
URL : https://hal.archives-ouvertes.fr/hal-00444076
From total store order to sequential consistency : A practical reduction theorem, International Conference on Interactive Theorem Proving, p.221, 1991. ,
, Parallel computer architecture : a hardware/software approach, 1999.
Principles and practices of interconnection networks, In ACM SIGPLAN Notices, vol.46, pp.67-78, 2004. ,
, Patterns in property specifications for finite-state verification. In Software Engineering, Proceedings of the 1999 International Conference on, vol.18, pp.124-131, 1983.
Using cache memory to reduce processormemory traffic, ACM SIGARCH Computer Architecture News, vol.11, issue.3, pp.124-131, 1983. ,
Cache consistency and sequential consistency, 1991. ,
Logic synthesis and verification algorithms, Hierarchical smp computer system. US Patent, vol.5, p.357, 1999. ,
Formal verification of the hal s1 system cache coherence protocol, Computer Design : VLSI in Computers and Processors, 1997. ICCD'97. Proceedings, pp.438-444, 1997. ,
Big. little system architecture from arm : saving power through heterogeneous multiprocessing and task context migration, Proceedings of the 49th Annual Design Automation Conference, pp.1143-1146, 2012. ,
Interconnections in multi-core architectures : Understanding mechanisms, overheads and scaling, 32nd International Symposium on Computer Architecture (ISCA'05), vol.400, pp.408-419, 1994. ,
How to make a multiprocessor computer that correctly executes multiprocess programs, IEEE transactions on computers, vol.100, issue.9, pp.690-691, 1979. ,
Scalable sharedmemory multiprocessing, 2014. ,
Memory coherence in shared virtual memory systems, ACM Transactions on Computer Systems (TOCS), vol.7, issue.4, pp.321-359, 1989. ,
Non-uniform memory access (numa), 2010. ,
Introduction to modeling and simulation, Proceedings of the 29th conference on Winter simulation, pp.7-13, 1997. ,
Multifacet's general execution-driven multiprocessor simulator (gems) toolset, ACM SIGARCH Computer Architecture News, vol.33, issue.4, pp.92-99, 2005. ,
The science of murphy's law, PROCEEDINGS-ROYAL INSTITUTION OF GREAT BRITAIN, vol.70, pp.75-96, 1999. ,
Design and application of embedded system based on arm7 lpc2104 processor in telemedicine, IEEE Engineering in Medicine and Biology 27th Annual Conference, pp.2187-2190, 2005. ,
Formal specification and verification of digital systems, 1993. ,
VHDL : Analysis and modeling of digital systems, 1997. ,
Simulating and evaluating interconnection networks with insee, Simulation Modelling Practice and Theory, vol.19, issue.1, pp.494-515, 2011. ,
Transaction level simulation of network-based computing systems, Computational Science and Computational Intelligence, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01568109
Methodology to verify, debug and evaluate performances of noc based interconnects, Proceedings of the 8th International Workshop on Network on Chip Architectures, pp.39-42, 2007. ,
, , 1999.
, Lisa-machine description language for cycle-accurate models of programmable dsp architectures, Proceedings of the 36th annual ACM/IEEE Design Automation Conference, pp.933-938
Cortex-r4 : A mid-range processor for deeply-embedded applications. ARM white paper, In ACM SIGARCH Computer Architecture News, vol.21, pp.290-298, 1988. ,
Layered crossbar for interconnection of multiple processors and shared memories, In ACM SIGARCH Computer Architecture News, vol.6, pp.128-138, 1985. ,
Improvements in multiprocessor system design, ACM SIGARCH Computer Architecture News, vol.13, pp.225-231, 1985. ,
The structural simulation toolkit, ACM SIGMETRICS Performance Evaluation Review, vol.38, issue.4, pp.37-42, 2011. ,
Overview of bus-based system-on-chip interconnections, IEEE International Symposium on, vol.2, p.633, 1990. ,
Synchronization and communication in the t3e multiprocessor, ACM SIGPLAN Notices, vol.31, pp.26-36, 1996. ,
Inside intel core microarchitecture (nehalem), A Symposium on High Performance Chips, vol.20, pp.473-530, 1982. ,
Design of a snoop filter for snoop based cache coherency protocols, Proceedings of the 43rd annual Design Automation Conference, pp.90-92, 2006. ,
Full system simulation of optically interconnected chip multiprocessors using gem5, Optical Fiber Communication Conference, pp.1-2, 2013. ,
The omnet++ discrete event simulation system, Proceedings of the European simulation multiconference (ESM'2001), vol.9, p.65, 2001. ,
Computer memory data merging technique for computers with write-back caches, International Conference on Cryptology in India, vol.5, pp.244-261, 1996. ,
Hierarchical cache/bus architecture for shared memory multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, pp.244-252, 1987. ,
Efficient broadcast scheme based on sub-network partition for many-core cmps on gem5 simulator, CCF National Conference on Compujter Engineering and Technology, pp.163-172, 2012. ,
Relaxed consistency and synchronization in parallel processors, 1992. ,