D. Cerovic, V. Piccolo, A. Amamou, and K. Haddadou, Offloading TRILL on a programmable card, pp.1-5, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01521453

V. D. Piccolo, D. Cerovic, and K. Haddadou, Synchronizing BRBs routing information to improve MLTP resiliency, 16th Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net), pp.1-5, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01632589

D. Cerovi?, V. Piccolo, A. Amamou, K. Haddadou, and G. Pujolle, Improving TRILL Mesh Network's Throughput Using Smart NICs, IEEE/ACM International Symposium on Quality of Service (IWQoS), 2018.

D. Cerovi?, V. Piccolo, A. Amamou, K. Haddadou, and G. Pujolle, Data Plane Offloading on a High-Speed Parallel Processing Architecture, IEEE 11th International Conference on Cloud Computing (CLOUD), pp.229-236, 2018.

D. Cerovi?, V. Piccolo, A. Amamou, K. Haddadou, and G. Pujolle, Fast Packet Processing: A Survey, IEEE Communications Surveys & Tutorials

D. Cerovi?, A. Amamou, K. Haddadou, and G. Pujolle, Data center's Parallel Processing Network Architecture Using Smart NICs, under review for IEEE Transactions on Parallel and Distributed Systems, p.133

A. Amamou, K. Haddadou, and G. Pujolle, A TRILL-based multi-tenant data center network, Computer Networks, vol.68, pp.35-53, 2014.

D. Medhi and K. Ramasamy, Network Routing: Algorithms, Protocols, and Architectures, 2007.

E. Kohler, R. Morris, B. Chen, J. Jannotti, and M. F. Kaashoek, The Click Modular Router, ACM Trans. Comput. Syst, vol.18, issue.3, pp.263-297, 2000.

L. Rizzo, Netmap: A Novel Framework for Fast Packet I/O, Proceedings of the 2012 USENIX Conference on Annual Technical Conference, ser. USENIX ATC'12, pp.9-9, 2012.

T. Marian, K. S. Lee, and H. Weatherspoon, NetSlices: Scalable Multi-core Packet Processing in User-space, Proceedings of the Eighth ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ser. ANCS '12, pp.27-38, 2012.

, PF_RING, 2018.

. Intel, Impressive Packet Processing Performance Enables Greater Workload Consolidation, Impressive-Packet-Processing-Performance-Enables-Greater-Workload-Consolidation, 2018.

S. Han, K. Jang, K. Park, and S. Moon, PacketShader: A GPU-accelerated Software Router, Proceedings of the ACM SIGCOMM 2010 Conference, ser. SIGCOMM '10, pp.195-206, 2010.

Y. Go, M. A. Jamshed, Y. Moon, C. Hwang, and K. Park, APUNet: Revitalizing GPU as Packet Processing Accelerator, 14th USENIX Symposium on Networked Systems Design and Implementation (NSDI 17), pp.83-96, 2017.

P. Bellows, J. Flidr, T. Lehman, B. Schott, and K. D. Underwood, GRIP: a reconfigurable architecture for host-based gigabit-rate packet processing, Field-Programmable Custom Computing Machines, pp.121-130, 2002.

M. B. Anwer, M. Motiwala, M. B. Tariq, and N. Feamster, SwitchBlade: A Platform for Rapid Deployment of Network Protocols on Programmable Hardware, Proceedings of the ACM SIGCOMM 2010 Conference, ser. SIGCOMM '10, pp.183-194, 2010.

, Open vSwitch* Enables SDN and NFV Transformation. Intel

B. Li, K. Tan, L. Luo, R. Luo, Y. Peng et al., ClickNP: Highly Flexible and High-performance Network Processing with Reconfigurable Hardware, 2016.

, OpenFastPath -Technical Overview, 2018.

, Accelerate networking innovation through programmable data plane -Removing switches from datacenters with TRILL/VNT and smartNIC, 2018.

B. D. De-dinechin, Kalray MPPA : Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor, 2015 IEEE Hot Chips 27 Symposium (HCS), pp.1-27, 2015.

E. Warnicke, OpenDataPlane (ODP) Users-Guide, 2018.

D. Cerovi?, V. D. Piccolo, A. Amamou, K. Haddadou, and G. Pujolle, Data plane offloading on a high-speed parallel processing architecture, 2018 IEEE 11th International Conference on Cloud Computing (CLOUD), pp.229-236, 2018.

M. Al-fares, A. Loukissas, and A. Vahdat, A Scalable, Commodity Data Center Network Architecture, SIGCOMM Comput. Commun. Rev, vol.38, issue.4, pp.63-74, 2008.

C. V. Networking, Cisco Global Cloud Index: Forecast and Methodology, 2016.

W. Wu, Packet Forwarding Technologies, 2007.

F. Intel-r-ethernet-switch, , 2018.

, The Future Is 40 Gigabit Ethernet. Cisco

I. Marinos, R. N. Watson, and M. Handley, Network stack specialization for performance, Proceedings of the 2014 ACM Conference on SIGCOMM, ser. SIGCOMM '14, pp.175-186, 2014.

L. Rizzo, Revisiting Network I/O APIs: The Netmap Framework, Queue, vol.10, issue.1, 2012.

T. Barbette, C. Soldani, and L. Mathy, Fast userspace packet processing, Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ser. ANCS '15, pp.5-16, 2015.

. Intel, DPDK: Data plane development kit, 2018.

. Solarflare, OpenOnload, 2018.

, PACKET_MMAP. Linux Kernel Contributors, 2018.

M. Dobrescu, N. Egi, K. Argyraki, B. Chun, K. Fall et al., Routebricks: Exploiting parallelism to scale software routers, Proceedings of the ACM SIGOPS 22Nd Symposium on Operating Systems Principles, ser. SOSP '09, pp.15-28, 2009.

W. Sun and R. Ricci, Fast and Flexible: Parallel Packet Processing with GPUs and Click, Proceedings of the Ninth ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ser. ANCS '13, pp.25-36, 2013.

J. Kim, S. Huh, K. Jang, K. Park, and S. B. Moon, The power of batching in the Click modular router, Asia-Pacific Workshop on Systems, APSys '12, p.14, 2012.

B. Chen and R. Morris, Flexible Control of Parallelism in a Multiprocessor PC Router, USENIX Annual Technical Conference, pp.333-346, 2001.

N. Shah, W. Plishker, K. Ravindran, and K. Keutzer, NP-Click: a productive software development approach for network processors, IEEE Micro, vol.24, issue.5, pp.45-54, 2004.

N. Mckeown, T. Anderson, H. Balakrishnan, G. Parulkar, L. Peterson et al., Openflow: Enabling innovation in campus networks, SIGCOMM Comput. Commun. Rev, vol.38, issue.2, pp.69-74, 2008.

J. C. Mogul, P. Yalag, J. Tourrilhes, R. Mcgeer, S. Banerjee et al., API design challenges for open router platforms on proprietary hardware, Proc. HotNets-VII, 2008.

O. E. Ferkouss, I. Snaiki, O. Mounaouar, H. Dahmouni, R. B. Ali et al., A 100Gig Network Processor platform for Openflow, 2011 7th International Conference on Network and Service Management, pp.1-4, 2011.

Y. K. Chang and F. Kuo, Towards optimized packet processing for multithreaded network processor, 2010 International Conference on High Performance Switching and Routing, pp.127-132, 2010.

T. Wolf and M. A. Franklin, Performance models for network processor design, IEEE Transactions on Parallel and Distributed Systems, vol.17, issue.6, pp.548-561, 2006.

E. Rubow, R. Mcgeer, J. C. Mogul, and A. Vahdat, Chimpp: a click-based programming and simulation environment for reconfigurable networking hardware, Proceedings of the 2010

, ACM/IEEE Symposium on Architecture for Networking and Communications Systems, p.36, 2010.

J. Naous, G. Gibb, S. Bolouki, and N. Mckeown, NetFPGA: Reusable Router Architecture for Experimental Research, Proceedings of the ACM Workshop on Programmable Routers for Extensible Services of Tomorrow, ser. PRESTO '08, pp.1-7, 2008.

M. Attig and G. Brebner, 400 Gb/s Programmable Packet Parsing on a Single FPGA, Architectures for Networking and Communications Systems (ANCS), pp.12-23, 2011.

A. Bitar, M. S. Abdelfattah, and V. Betz, Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA, Field Programmable Technology (FPT), 2015 International Conference on, pp.24-31, 2015.

G. Vasiliadis, L. Koromilas, M. Polychronakis, and S. Ioannidis, Design and Implementation of a Stateful Network Packet Processing Framework for GPUs, IEEE/ACM Trans. Netw, vol.25, issue.1, pp.610-623, 2017.

. Berten, White paper -GPU vs FPGA Performance Comparison, 2018.

L. Rizzo and G. Lettieri, VALE, a Switched Ethernet for Virtual Machines, Proceedings of the 8th International Conference on Emerging Networking Experiments and Technologies, ser. CoNEXT '12, pp.61-72, 2012.

L. Rizzo, G. Lettieri, and V. Maffione, Speeding up packet I/O in virtual machines, Architectures for Networking and Communications Systems, pp.47-58, 2013.

S. Garzarella, G. Lettieri, and L. Rizzo, Virtual device passthrough for high speed VM networking, 2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pp.99-110, 2015.

J. Hwang, K. K. Ramakrishnan, and T. Wood, NetVM: High Performance and Flexible Networking Using Virtualization on Commodity Platforms, IEEE Transactions on Network and Service Management, vol.12, issue.1, pp.34-47, 2015.

B. Pfaff, J. Pettit, T. Koponen, K. Amidon, M. Casado et al., Extending networking into the virtualization layer, Proc. of workshop on Hot Topics in Networks (HotNets-VIII), 2009.

G. Robin, Open vSwitch with DPDK Overview. Intel, 2018.

W. Xia, P. Zhao, Y. Wen, and H. Xie, Infrastructure and Operations, A Survey on Data Center Networking (DCN, vol.19, issue.1, pp.640-656, 2017.

D. E. 3rd, D. G. Dutt, S. Gai, R. Perlman, and A. Ghanwani, Routing Bridges (RBridges): Base Protocol Specification, RFC, vol.6325, 2011.

, ktrill -TRILL implementation in the Linux Kernel, 2017.

D. Cerovi?, V. D. Piccolo, A. Amamou, K. Haddadou, and G. Pujolle, Fast packet processing: A survey, IEEE Communications Surveys Tutorials, 2018.

, The Juniper Networks QFabric Architecture: A Revolution in Data Center Network Design Flattening the Data Center Architecture, 2018.

S. Hooda, S. Kapadia, and P. Krishnan, Using TRILL, FabricPath, and VXLAN: Designing Massively Scalable Data Centers (MSDC) with Overlays, ser. Networking Technology. Pearson Education, 2014.

, Cisco Data Center Spine-and-Leaf Architecture: Design Overview White Paper, 2018.

, Ethernet Fabrics and Brocade VCS Technology: Networking for the Virtualized Data Center, 2018.

, 1aq -Shortest Path Bridging, vol.802, 2018.

D. Allan and N. Bragg, 802.1aq Shortest Path Bridging Design and Evolution: The Architect's Perspective, 2012.

R. Van-der-pol, TRILL and IEEE 802.1aq Overview, 2018.

C. R. Meiners, A. X. Liu, and E. Torng, Hardware Based Packet Classification for High Speed Internet Routers, 2010.

R. Ramaswamy, N. Weng, and T. Wolf, Characterizing network processing delay, Global Telecommunications Conference, 2004. GLOBECOM '04. IEEE, vol.3, pp.1629-1634, 2004.

H. Asai, Where Are the Bottlenecks in Software Packet Processing and Forwarding?: Towards High-performance Network Operating Systems, Proceedings of The Ninth International Conference on Future Internet Technologies, ser. CFI '14, vol.5, pp.1-5, 2014.

L. Rizzo, L. Deri, and A. Cardigliano, 10 Gbit/s Line Rate Packet Processing Using Commodity Hardware: Survey and new Proposals, 2012.

S. Networking, Eliminating the Receive Processing Bottleneck-Introducing RSS, Microsoft WinHEC, 2004.

L. Deri, nCap: wire-speed packet capture and transmission, Workshop on End-to-End Monitoring Techniques and Services, pp.47-55, 2005.

, Now the Tock Next Generation Intel Microarchitecture (Nehalem). Intel

N. Egi, M. Dobrescu, J. Du, K. Argyraki, B. Chun et al., Understanding the packet processing capability of multi-core servers, Intel Technical Report, Tech. Rep, 2009.

M. Miao, W. Cheng, F. Ren, and J. Xie, Smart Batching: A Load-Sensitive Self-Tuning Packet I/O Using Dynamic Batch Sizing, 2016 IEEE 18th International Conference on High Performance Computing and Communications; IEEE 14th International Conference on Smart City

, IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS), pp.726-733, 2016.

L. Rizzo, OVS: accelerating the datapath through netmap/VALE, 2018.

L. Deri, N. S. , V. D. Km, and L. L. Figuretta, Improving Passive Packet Capture: Beyond Device Polling, 2004.

J. C. Mogul and K. K. Ramakrishnan, Eliminating receive livelock in an interrupt-driven kernel, ACM Trans. Comput. Syst, vol.15, issue.3, pp.217-252, 1997.

J. H. Salim, When NAPI comes to town, Linux 2005 Conf, 2005.

, 6WINDGate Packet Processing Software For COTS Servers Scalable Data Plane Performance For Multicore Platforms, 6WIND, 2018.

J. Nickolls, GPU parallel computing architecture and CUDA programming model, 2007 IEEE Hot Chips 19 Symposium (HCS), pp.1-12, 2007.

K. Fatahalian and M. Houston, A Closer Look at GPUs, Commun. ACM, vol.51, issue.10, pp.50-57, 2008.

A. Kalia, D. Zhou, M. Kaminsky, and D. G. Andersen, Raising the Bar for Using GPUs in Software Packet Processing, Proceedings of the 12th USENIX Conference on Networked Systems Design and Implementation, ser. NSDI'15, pp.409-423, 2015.

V. Volkov, Understanding latency hiding on gpus, 2016.

G. Vasiliadis, L. Koromilas, M. Polychronakis, and S. Ioannidis, GASPP: A GPU-Accelerated Stateful Packet Processing Framework, 2014 USENIX Annual Technical Conference (USENIX ATC 14), pp.321-332, 2014.

S. Gallenmüller, P. Emmerich, F. Wohlfart, D. Raumer, and G. Carle, Comparison of frameworks for high-performance packet IO, 2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pp.29-38, 2015.

T. Hudek and D. Macmichael, Introduction to the NDIS PacketDirect Provider Interface, 2018.

S. Gueron, Speeding up CRC32C computations with Intel CRC32 instruction, Information Processing Letters, vol.112, issue.5, pp.179-185, 2012.

. Intel, Intel R SSE4 Programming Reference, p.61, 2018.

, Click Modular Router, 2018.

, RouteBricks, 2018.

, FastClick, 2018.

, Snap, 2018.

, NetSlice, 2018.

, PF_RING, 2018.

, DPDK, 2018.

. Packetshader, , 2018.

. Packetshader-website, , 2018.

M. Bourguiba, K. Haddadou, and G. Pujolle, A Container-Based Fast Bridge for Virtual Routers on Commodity Hardware, 2010 IEEE Global Telecommunications Conference GLOBECOM 2010, pp.1-6, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01289180

M. Bourguiba, K. Haddadou, I. E. Korbi, and G. Pujolle, A Container-Based I/O for Virtual Routers: Experimental and Analytical Evaluations, 2011 IEEE International Conference on Communications (ICC), pp.1-6, 2011.
URL : https://hal.archives-ouvertes.fr/hal-01282504

P. Barham, B. Dragovic, K. Fraser, S. Hand, T. Harris et al., Xen and the art of virtualization, Proceedings of the Nineteenth ACM Symposium on Operating Systems Principles, ser. SOSP '03, pp.164-177, 2003.

M. Bourguiba, K. Haddadou, I. E. Korbi, and G. Pujolle, Improving Network I/O Virtualization for Cloud Computing, IEEE Transactions on Parallel and Distributed Systems, vol.25, issue.3, pp.673-681, 2014.

F. Bellard, QEMU, a fast and portable dynamic translator, USENIX Annual Technical Conference, FREENIX Track, pp.41-46, 2005.

A. Kivity, Y. Kamay, D. Laor, U. Lublin, and A. Liguori, KVM: the Linux Virtual Machine Monitor, Proceedings of the 2007 Ottawa Linux Symposium (OLS'-07, 2007.

V. Maffione, L. Rizzo, and G. Lettieri, Flexible virtual machine networking using netmap passthrough, 2016 IEEE International Symposium on Local and Metropolitan Area Networks (LANMAN), pp.1-6, 2016.

R. Russell, Virtio: Towards a De-facto Standard for Virtual I/O Devices, SIGOPS Oper. Syst. Rev, vol.42, issue.5, pp.95-103, 2008.

J. Tseng, R. Wang, J. Tsai, Y. Wang, and T. C. Tai, Accelerating Open vSwitch with Integrated GPU, Proceedings of the Workshop on Kernel-Bypass Networks, ser. KBNets '17, pp.7-12, 2017.

J. Tseng, R. Wang, J. Tsai, S. Edupuganti, A. W. Min et al., Exploiting integrated GPUs for network packet processing workloads, 2016 IEEE NetSoft Conference and Workshops (NetSoft), pp.161-165, 2016.

R. Kawashima, S. Muramatsu, H. Nakayama, T. Hayashi, and H. Matsuo, A Host-Based Performance Comparison of 40G NFV Environments Focusing on Packet Processing Architectures and Virtual Switches, 2016 Fifth European Workshop on Software-Defined Networks (EWSDN), pp.19-24, 2016.

E. Kohler, The Click modular router, 2001.

, Altera SDK for OpenCL, 2018.

S. Environment, , 2018.

, Vivado Design Suite, 2018.

, NVIDIA CUDA SDK 3.0, 2018.

, Intel -Linux ixgbe* Base Driver Overview and Installation, 2018.

A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides et al., A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services, Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser. ISCA '14, pp.13-24, 2014.

, Syskonnect gigabit ethernet card, 2018.

&. Xmacii, , 2018.

J. Corbet and G. Kroah-hartman, Linux kernel development: How fast it is going, who is doing it, what they are doing, and who is sponsoring the work, The Linux Foundation, pp.1-19, 2016.

E. Warnicke and . Io-intro, , 2018.

, Vector Packet Processing (VPP), 2018.

, VPP/What is VPP, 2018.

, VPP on OpenDataPlane enabled SmartNICs, 2018.

, OpenDataPlane (ODP) Project, 2018.

, PCIe NIC optimised implementation (odp-dpdk), 2018.

, OpenDataPlane DPDK platform implementation, 2018.

, OpenFastPath, 2018.

P. Bosshart, D. Daly, G. Gibb, M. Izzard, N. Mckeown et al., P4: Programming Protocol-independent Packet Processors, SIGCOMM Comput. Commun. Rev, vol.44, issue.3, pp.87-95, 2014.

,

H. Wang, R. Soulé, H. T. Dang, K. S. Lee, V. Shrivastav et al., P4FPGA: A Rapid Prototyping Framework for P4, Proceedings of the Symposium on SDN Research, ser. SOSR '17, pp.122-135, 2017.

,

P. Li and Y. Luo, P4GPU: Accelerate Packet Processing of a P4 Program with a CPU-GPU Heterogeneous Architecture, Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, ser. ANCS '16, pp.125-126, 2016.

P. Benácek, V. Pu, and H. Kubátová, P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.148-155, 2016.

A. Sivaraman, C. Kim, R. Krishnamoorthy, A. Dixit, and M. Budiu, DC.P4: Programming the Forwarding Plane of a Data-center Switch, Proceedings of the 1st ACM SIGCOMM Symposium on Software Defined Networking Research, ser. SOSR '15, vol.2, pp.1-2, 2015.

S. Laki, D. Horpácsi, P. Vörös, R. Kitlei, D. Leskó et al., High Speed Packet Forwarding Compiled from Protocol Independent Data Plane Specifications, Proceedings of the 2016 ACM SIGCOMM Conference, ser. SIGCOMM '16, pp.629-630, 2016.

A. Bhardwaj, A. Shree, V. B. Reddy, and S. Bansal, A Preliminary Performance Model for Optimizing Software Packet Processing Pipelines, Proceedings of the 8th Asia-Pacific Workshop on Systems, ser. APSys '17, vol.26, pp.1-26, 2017.

G. Bianchi, M. Bonola, A. Capone, and C. Cascone, OpenState: Programming Platform-independent Stateful Openflow Applications Inside the Switch, SIGCOMM Comput. Commun. Rev, vol.44, issue.2, pp.44-51, 2014.

S. Pontarelli, M. Bonola, G. Bianchi, A. Capone, and C. Cascone, Stateful OpenFlow: Hardware proof of concept, 2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR), pp.1-8, 2015.

, BESS (Berkeley Extensible Software Switch), 2018.

S. Han, K. Jang, A. Panda, S. Palkar, D. Han et al., SoftNIC: A Software NIC to Augment Hardware, 2015.

, QFabric System Overview, 2018.

. Cisco-fabricpath, , 2018.

, VCS Fabrics overview, 2018.

, Shortest Path Bridging IEEE 802, vol.1, 2018.

, The Great Debate: TRILL Versus 802.1aq (SBP), 2018.

Y. Liao, D. Yin, and L. Gao, PdP: Parallelizing Data Plane in Virtual Network Substrate, Proceedings of the 1st ACM Workshop on Virtualized Infrastructure Systems and Architectures, ser. VISA '09, pp.9-18, 2009.

J. Kim, S. Huh, K. Jang, K. Park, and S. Moon, The Power of Batching in the Click Modular Router, Proceedings of the Asia-Pacific Workshop on Systems, ser. APSYS '12, vol.14, pp.1-14, 2012.

L. Rizzo, M. Carbone, and G. Catalli, Transparent acceleration of software packet forwarding using netmap, 2012 Proceedings IEEE INFOCOM, pp.2471-2479, 2012.

D. Blythe, Rise of the Graphics Processor, Proceedings of the IEEE, vol.96, issue.5, pp.761-778, 2008.

J. D. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krüger et al., A survey of general-purpose computation on graphics hardware, Computer Graphics Forum, vol.26, issue.1, pp.80-113, 2007.

E. Papadogiannaki, L. Koromilas, G. Vasiliadis, and S. Ioannidis, Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures, IEEE/ACM Transactions on Networking, vol.25, issue.3, pp.1593-1606, 2017.

Z. Zheng, J. Bi, H. Yu, C. Sun, and J. Wu, BLOP: Batch-Level Order Preserving for GPU-Accelerated Packet Processing, Proceedings of the SIGCOMM Posters and Demos, ser. SIGCOMM Posters and Demos '17, pp.136-137, 2017.

F. Fusco, M. Vlachos, X. Dimitropoulos, and L. Deri, Indexing million of packets per second using gpus, Proceedings of the 2013 Conference on Internet Measurement Conference, ser. IMC '13, pp.327-332, 2013.

J. D. Owens, M. Houston, D. Luebke, S. Green, J. E. Stone et al., GPU Computing, Proceedings of the IEEE, vol.96, issue.5, pp.879-899, 2008.

M. Garland, Parallel computing with CUDA, Parallel Distributed Processing (IPDPS), 2010 IEEE International Symposium on, pp.1-1, 2010.

Y. Zhu, Y. Deng, and Y. Chen, Hermes: An integrated CPU/GPU microarchitecture for IP routing, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp.1044-1049, 2011.

S. Mu, X. Zhang, N. Zhang, J. Lu, Y. S. Deng et al., IP routing processing with graphic processors, pp.93-98, 2010.

B. Betkaoui, D. B. Thomas, and W. Luk, Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing, Field-Programmable Technology (FPT), 2010 International Conference on, pp.94-101, 2010.

S. Mittal and J. S. Vetter, A Survey of Methods for Analyzing and Improving GPU Energy Efficiency, ACM Comput. Surv, vol.47, issue.2, pp.1-19, 2014.

D. Bacon, R. Rabbah, and S. Shukla, FPGA Programming for the Masses, Queue, vol.11, issue.2, 2013.

T. Rinta-aho, M. Karlstedt, and M. P. Desai, The Click2NetFPGA Toolchain, Proceedings of the 2012 USENIX Conference on Annual Technical Conference, ser. USENIX ATC'12, pp.7-7, 2012.

G. Gibb, J. W. Lockwood, J. Naous, P. Hartke, and N. Mckeown, NetFPGA -An Open Platform for Teaching How to Build Gigabit-Rate Network Switches and Routers, IEEE Transactions on Education, vol.51, issue.3, pp.364-369, 2008.

J. W. Lockwood, N. Mckeown, G. Watson, G. Gibb, P. Hartke et al., NetFPGA-An Open Platform for Gigabit-Rate Network Switching and Routing, Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education, ser. MSE '07, pp.160-161, 2007.

,

N. Zilberman, Y. Audzevich, G. A. Covington, and A. W. Moore, NetFPGA SUME: Toward Research Commodity 100Gb/s, 2014.

N. Zilberman, Y. Audzevich, G. Kalogeridou, N. M. Bojan, J. Zhang et al., NetF-PGA -rapid prototyping of high bandwidth devices in open source, 2015 25th International Conference on Field Programmable Logic and Applications (FPL), pp.1-1, 2015.

M. Labrecque, J. G. Steffan, G. Salmon, M. Ghobadi, and Y. Ganjali, NetThreads: Programming NetFPGA with threaded software, 2009.

P. Varga, L. Kovács, T. Tóthfalusi, and P. Orosz, C-GEP: 100 Gbit/s capable, FPGA-based, reconfigurable networking equipment, 2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR), pp.1-6, 2015.

B. Wheeler, A new era of network processing, The Linley Group, 2013.

J. Shim, J. Kim, K. Lee, and S. Moon, Knapp: A packet processing framework for manycore accelerators, 2017 IEEE 3rd International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), pp.57-64, 2017.

G. Chrysos, Intel R Xeon Phi coprocessor (codename Knights Corner), 2012 IEEE Hot Chips 24 Symposium (HCS), pp.1-31, 2012.

, OpenDataPlane port for the MPPA platform, p.16, 2017.

A. Amamou, M. Bourguiba, K. Haddadou, and G. Pujolle, DBA-VM: Dynamic bandwidth allocator for virtual machines, 2012 IEEE Symposium on Computers and Communications (ISCC), pp.0-713, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00857388

R. Intel and . Ethernet, Controller 10 Gigabit and 40 Gigabit XL710 Brief

C. E. Leiserson, Fat-trees: Universal networks for hardware-efficient supercomputing, IEEE Transactions on Computers, vol.34, issue.10, pp.892-901, 1985.

Y. Liu, J. Han, and H. Du, A hypercube-based scalable interconnection network for massively parallel computing, Journal of Computers, vol.3, issue.10, pp.58-65, 2008.

A. Louri, B. Weech, and C. Neocleous, A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel computing, IEEE Transactions on Parallel and Distributed Systems, vol.9, issue.5, pp.497-512, 1998.

, Cavium ThunderX implimentation of ODP, 2018.

, QorIQ -sdk/odp.git -Open Data Plane Interface Implementation, 2018.

, TIs Keystone2 with multi core System-on-Chip Cortex A15 and TMS320C66x DSP hardware acceleration for ODP, 2018.

, OpenDataPlane Marvell implementation odp-marvell

/. Marvellembeddedprocessors, , 2018.

D. E. 3rd, R. Perlman, A. Ghanwani, H. Yang, and V. Manral, Transparent Interconnection of Lots of Links (TRILL): Adjacency, RFC, vol.7177, 2014.

D. E. 3rd, M. Zhang, R. Perlman, A. Banerjee, A. Ghanwani et al., Transparent Interconnection of Lots of Links (TRILL): Clarifications, Corrections, and Updates, RFC, vol.7780, 2016.

, Information technology -Telecommunications and information exchange between systems -Intermediate System to Intermediate System intra-domain routeing information exchange protocol for use in conjunction with the protocol for providing the connectionless-mode network service, ISO/IEC 10589:2002(E), 2002.