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Développement de procédés de gravure des espaceurs Si3N4 pour les technologies sub-10nm

Abstract : Integrated circuits never stop shrinking to satisfy the increasing demand in computing power and mobile device integration. In this race, the conventional « planar » or 2D architecture of CMOS components tends to reach its limits in terms of electrostatic conduction channel control reliability since the 22nm technology node was reached. To solve this issue, « FinFET » and stacked nanowires (3D) architectures came into existence. These complicated new architectures necessitate overcoming new constraints during the component manufacturing. One of the most challenging steps concerns the nitride spacer etching. With a 3D architecture, the over-etch to apply is indeed, much more significant (>300%) and requires that high Si3N4 / Si selectivity is achieved while damages on silicon are avoided at the same time. Firstly, this thesis work focuses on the conventional spacer etching process and its limitations for 3D applications. Then the study focuses on the development of an innovative etching process based on alternative steps of deposition and etching. It is seen that an oxide formation preferentially on silicon combined with a nitride etching step allows us to reach a selectivity as high as 53. The developed process has been tested on patterned wafers and has demonstrated the concept validity. At the end of this study, an alternative technique based on argon implantation followed by wet etching is discussed and opens an interesting perspective.
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Submitted on : Thursday, July 23, 2020 - 5:19:26 PM
Last modification on : Wednesday, October 14, 2020 - 4:10:01 AM


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  • HAL Id : tel-02905800, version 1




Vincent Ah-Leung. Développement de procédés de gravure des espaceurs Si3N4 pour les technologies sub-10nm. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes [2020-..], 2020. Français. ⟨NNT : 2020GRALT002⟩. ⟨tel-02905800⟩



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