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, Ce passage d'une interconnexion horizontale à une interconnexion verticale est très prometteur en termes de rapidité et de performances globales (délai RC, consommation et facteur de forme). D'autre part, pour le développement technologique de l'intégration 3D avant la production des plaques (wafers) de 300 mm avec toutes les couches FEOL et BEOL, plusieurs plaques (short-loop) doivent être réalisées pour permettre la caractérisation incrémentale et le test structurel des interconnexions 3D afin d'évaluer la performances électriques (R, L, C?). D'autre part, le test des circuits d'application consiste à ajouter des fonctionnalités de testabilité (Boundary-Scan-Cells (BSC), Built-In-Self-Test (BIST) et des chaînes de scan ?) pour le test fonctionnel du circuit 3D (y compris les puces empilées et les interconnexions 3D). L'architecture DFT (Design-For-Test) ajoutée facilite le développement et l'application des tests de fabrication au circuit conçu. Par rapport aux interconnexions µ-bumps, ? Xlsx write: ? Wafer map: ? Box plot: Résumé L'intégration de plusieurs puces dans un empilement 3D constitue un autre moyen d'avancer dans le domaine « More-than-Moore ». L'intégration 3D consiste à interconnecter les circuits intégrés en trois dimensions à l'aide des interconnexions inter-puces (µ-bumps ou Cu-Cu interconnexions) et les TSVs (Through Silicon Vias)

, Une étude théorique a ensuite été réalisée pour définir l'infrastructure DFT la plus optimisée en fonction de la valeur du pas minimal acceptable pour un noeud technologique donné, afin de garantir la testabilité des circuits 3D haute densité. De plus, une architecture DFT optimisée permettant un test avant et après assemblage des circuits 3D haute densité (Mémoiresur-Logique) a été proposée. Enfin, pour évaluer les performances des circuits 3D haute densité, deux BISTs complémentaires ont été mis en oeuvre dans un circuit d'application utilisant la même structure de test de désalignement développée ci-dessus et une chaîne d, plus les défauts de fabrication et de liaison ont un impact important sur le rendement et les performances. Des défauts tels que le désalignement, des « µ-voids » et des défauts de contact à la surface du cuivre peuvent affecter considérablement les caractéristiques électriques et la durée de vie du circuit 3D

, Mots clés: 3D-IC, interconnexions haute densité, collage hybride Cu-Cu, désalignement, « µvoid », véhicules de test