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Test and characterization of 3D high-density interconnects

Abstract : The integration of multiple chips in a 3D stack serves as another path to move forward in the more-than-Moore domain. 3D integration technology consists in interconnecting the integrated circuits in three dimensions using inter-die interconnects (μ-bumps or Cu-Cu interconnects) and Through Silicon Vias (TSV). This changeover from horizontal to vertical interconnection is very promising in terms of speed and overall performances (RC delay, power consumption and form factor). On the other side, for technology development of 3D integration before the production of the 300 mm wafers with all FEOL and BEOL layers, several short-loops must been carried out to enable incremental characterization and structural test of 3D interconnects in order to evaluate the electrical performances (R, L, C …). In the other hand, the test of application circuits consists in adding testability features (Boundary-Scan-Cells (BSCs), Built-In-Self-Test (BIST) and scan chains …) for functional test of the hardware product design (including the different stacked dies and the 3D interconnections) . The added Design-For-Test (DFT) architecture make it easier to develop and apply manufacturing tests to the designed hardware. Compared to μ-bumps, Cu-Cu hybrid bonding provides an alternative for future scaling below 10μm pitch with improved physical properties but that generates new challenges for test and characterization; the smaller the Cu pad size, the more the fabrication and bonding defects have an important impact on yield and performance. Defects such as bonding misalignment, micro-voids and contact defects at the copper surface, can affect the electrical characteristics and the life time of 3D-IC considerably. Moreover, test infrastructure insertion for HD 3D-ICs presents new challenges because of the high interconnects density and the area cost for test features. Hence, in this thesis work, an innovative misalignment test structure has been developed and implemented in short-loop way. The proposed approach allows to measure accurately bonding misalignment, know the misalignment direction and estimate the contact resistance. Afterwards, a theoretical study has been performed to define the most optimized DFT infrastructure depending on the minimum acceptable pitch value for a given technology node to ensure the testability of high-density 3D-ICs. Furthermore, an optimized DFT architecture allowing pre-bond and post-bond for high-bandwidth and high-density 3D-IC application (SRAM-on-Logic) has been proposed. Finally, to assess performance of HD 3D-ICs, two complementary BISTs has been implemented in an application circuit using the same misalignment test structure developed above and a daisy chain of Cu-Cu interconnects. Using test results, on the one hand, the impact of misalignment defect on the propagation delay has been studied and on the other hand full open and μ-voids defects at the contact surface level has been detected.
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Imed Jani. Test and characterization of 3D high-density interconnects. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2019. English. ⟨NNT : 2019GREAT094⟩. ⟨tel-02634259⟩

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