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Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications

Abstract : In recent years, a number of physical and economical barriers have emerged in the race for miniaturization and speed of integrated circuits. To circumvent these issues, new processes and architectures are continuously developed. In particular, a progressive shift towards 3D integration strategies is currently observed in the semiconductor industry as an alternative path to further transistor downscaling. This innovative approach consists in combining chips of different technologies or different functionalities into a single module. A possible strategy to realize such heterogeneous systems is to stack chips on top of each other instead of tiling them on the plane, enabling considerable benefits in terms of compactness and versatility, but also increased performance. This is especially true for image sensor chips, for which vertical stacking allows the incorporation of additional functionalities such as advanced image signal processing. Among various methods to achieve direct vertical interconnections between stacked chips, a promising method is Cu/SiO2 hybrid bonding, enabling simultaneous mechanical and electrical connection with a submicron interconnection pitch mostly limited by photolithography resolution and alignment accuracy.The mechanical integrity of the different electrical connection elements for such a 3D integrated imager-on-logic device is of critical importance. The aim of this thesis is to investigate the mechanical robustness of this relatively new architecture in semiconductor manufacturing during its fabrication, aiming to address a number of possible issues from a thermomechanical perspective. In this work, thermomechanical stresses building up in the image sensor during chip processing and assembly onto a package are investigated, and the interactions between the different system components analyzed. The mechanical integrity of several key structures is studied, namely (i) interconnection pads at the hybrid bonding interface between the imager/logic chips, (ii) bondpad structures below the wires connecting the imager to the package substrate, and (iii) semiconductor devices in the image sensor, through in-situ evaluation of process-induced mechanical stresses using doped Si piezoresistive stress sensors. To do so, for each item a combined numerical and experimental approach was adopted, using morphological, mechanical and electrical characterizations, then correlated or extended by thermomechanical finite element analyses, allowing to secure product integration from a thermomechanical perspective.
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Clément Sart. Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications. Chemical and Process Engineering. Université Grenoble Alpes, 2019. English. ⟨NNT : 2019GREAI084⟩. ⟨tel-02517015v2⟩

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