Skip to Main content Skip to Navigation

An Efficient Computer-Aided Design Methodology for FPGA&ASIC High-Level Power Estimation Based on Machine Learning

Abstract : Nowadays, advanced digital systems are required to address complex functionnalities in a very wide range of applications. Systems complexity imposes designers to respect different design constraints such as the performance, area, power consumption and the time-to-market. The best design choice is the one that respects all of these constraints. To select an efficient design, designers need to quickly assess the possible architectures. In this thesis, we focus on facilitating the evaluation of the power consumption for both signal processing and hardware design engineers, so that it is possible to maintain fast, accurate and flexible power estimation. We present NeuPowas a system-level FPGA/ASIC power estimation method based on machine learning. We exploit neural networks to aid the designers in exploring the dynamic power consumption of possible architectural solutions. NeuPow relies on propagating the signals throughout connected neural models to predict the power consumption of a composite system at high-level of abstractions. We also provide an upgraded version that is frequency aware estimation. To prove the effectiveness of the proposed methodology, assessments such as technology and scalability studies have been conducted on ASIC and FPGA. Results show very good estimationaccuracy with less than 10% of relative error independently from the technology and the design size. NeuPow maintains high design productivity, where the simulation time obtained is significantly improved compared to those obtained with conventional design tools.
Document type :
Complete list of metadatas

Cited literature [125 references]  Display  Hide  Download
Contributor : Abes Star :  Contact
Submitted on : Monday, March 23, 2020 - 5:38:13 PM
Last modification on : Friday, October 23, 2020 - 4:48:53 PM
Long-term archiving on: : Wednesday, June 24, 2020 - 3:51:48 PM


Version validated by the jury (STAR)


  • HAL Id : tel-02516046, version 1


Yehya Nasser. An Efficient Computer-Aided Design Methodology for FPGA&ASIC High-Level Power Estimation Based on Machine Learning. Electronics. INSA de Rennes, 2019. English. ⟨NNT : 2019ISAR0014⟩. ⟨tel-02516046⟩



Record views


Files downloads