O. Weber, High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding, IEEE IEDM, 2008.

P. Flatresse, Body Biasing techniques in UTBB FDSOI technology, NEWCAS, 2015.

J. David, A 3 GHz dual core processor ARM cortex TM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization, IEEE Journ. of Solid-State Circuits, vol.49, pp.812-826, 2014.

R. E. Best, Phase-locked loops : design, simulation, and applications, 2003.

A. Hadjichristos, Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS, IEEE International Solid-State Circuits Conference, pp.118-119, 2009.

B. B. Purkayastha-&-k and . Sarma, A digital phase locked loop based signal and symbol recovery system for wireless channel, 2015.

M. Curtin and P. O. Dialogue, Phase-Locked Loops for High-Frequency Receivers and Transmitters, Analog dialogue, 1999.

N. M. Rau, T. Oberst, R. Lares, A. Rotherme, &. et al., Clock/data recovery PLL using half-frequency clock, IEEE J. Solid-State Circuits, vol.32, issue.7, pp.1156-1159, 1997.

K. Dalmia, Clock and data recovery PLL based on parallel architecture, US Patent n° US6417698B1, 2000.

J. G. Alexovich-&-r and . On, Effect of PLL frequency synthesizer in FSK frequency-hopped communications, IEEE Trans. Commun, vol.37, pp.268-276, 1989.

R. P. Xiu, &. J. Li, and . Meiners, A novel all-digital PLL with software adaptive filter, IEEE Journ. of Solid-State Circuits, vol.39, pp.476-483, 2004.


J. Borremans, A 86 MHz-12 GHz digital-intensive PLL for software-defined radios, using a 6 fJ/step TDC in 40 nm digital CMOS, IEEE J. Solid-State Circuits, vol.45, pp.2116-2129, 2010.

J. M. Patrin-&-d and . Li, Characterizing jitter histograms for clock and datacom applications, 2004.

D. H. Wolaver, Phase-locked loop circuit design, 1991.

U. Moon, K. &. Mayaram, and . On, Spectral analysis of time-domain phase jitter measurements, IEEE Trans. Circuits Syst. II Analog Digit. Signal Process, vol.49, issue.5, pp.321-327, 2002.

J. Lee, H. Y. Kim-&-c, and . Consumer, Spread spectrum clock generation for reduced electromagnetic interference in consumer electronics devices, IEEE Trans. Consum. Electron, vol.56, issue.2, pp.844-847, 2010.

, Clock Jitter Definitions and Measurement Methods, 2014.

V. K. Sharma, Analysis and estimation of jitter sub-components, 2014.

W. Kester, Converting Oscillator Phase Noise to Time Jitter, 2009.

D. B. Lesson, A simple model of feedback oscillator noise spectrum, proc. IEEE, vol.54, pp.329-330, 1966.

B. Razavi, A Study of Phase Noise in CMOS OSC.pdf, vol.31, pp.331-343, 1996.

A. Hajimiri, S. Limotyrakis, and T. L. , Jitter and phase noise in ring oscillators, IEEE J. Solid-State Circuits, vol.34, issue.6, pp.790-804, 1999.

A. Hajimiri, A general theory of phase noise in electrical oscillators, IEEE J. Solid-State Circuits, vol.33, issue.2, pp.179-194, 1998.

A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, Phase-Locking High-Performance Syst, vol.33, pp.189-204, 2003.

J. S. Demir and A. Mehrotra, Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation, 1998.

K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers, 2012.

P. Kinget, Integrated GHz Voltage Controlled Oscillators, Analog Circuit Design, pp.353-381, 1999.

H. Wang, GHz back-gate tuned VCO in 0.35 ?m CMOS, IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC, pp.406-407, 1999.

M. S. De-cock, A CMOS 10GHz voltage controlled LC-oscillator with integrated high-Q inductor, Proc. 27th Eur. Solid-State Circuits Conf. IEEE, pp.498-501, 2001.

F. and B. Abdeljelil, Contribution à la conception et à la réalisation de synthétiseurs de fréquence pour communications satellitaires, 2010.

A. Fonseca, Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm, 2015.

W. Zhu and &. Ma, Investigating the Effects of the Number of Stages on Phase Noise in CMOS Ring Oscillators, International Symposium on Integrated Circuits, pp.612-615, 2009.

A. H. Hajimiri-&-t and . Lee, Phase-Locking High-Performance Syst. From Devices to Archit, vol.33, pp.189-204, 2003.

J. G. Maneatis-&-m and . Horowitz, Precise delay generation using coupled oscillators, vol.273, pp.118-119, 1993.

B. Van-der-pol, The Nonlinear Theory of Electric Oscillations, Proc. IRE, vol.22, pp.1051-1086, 1934.

B. Razavi, RF Microelectronics, 2011.

Y. Lai, Spectre Circuit Simulator User Guide, pp.1069-1072, 2009.

K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers, 2015.

H. Masten, Ring oscillator design in 32nm CMOS with frequency and power analysis for changing supply voltage

, Types-of-Scaling | CMOS-Layout-Design | Electronics Tutorial, p.18, 2018.

S. Wong, C. Andre, and &. Salama, Impact of Scaling on MOS Analog Performance, IEEE J. Solid-State Circuits, vol.18, issue.1, pp.106-114, 1983.

, EE141-Fall 2002 Impact of Technology Scaling

G. Jacquemod, Z. Wei, Y. Leduc, and C. Jacquemod, New QVCO design using UTBB FDSOI technology, European Workshop on Microelectronics Education (EWME), pp.1-4, 2016.

B. Razavi, Phase-locking in high-performance systems : from devices to architectures, pp.978-0471447276, 2003.

B. Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovcry Circuits: Theory and Design, pp.978-0780311497, 2008.

B. Razavi, Design of Analog CMOS Integrated Circuits, pp.978-0072380323, 2000.

C. Toumazou, F. Lidgey, and &. Haigh, Analogue IC design: the current-mode approach, The Institution of Engineering and Technology, pp.978-0863412974, 1993.

R. Keim, MOSFET Channel-Length Modulation

G. Palumbo, On the high-frequency response of CMOS cascode current mirror, 1994.

B. Gilbert, Analogue IC design: the current-mode approach, pp.978-0863412974, 1993.

T. Serrano and &. Linares-barranco, The active-input regulated-cascode current mirror, IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol.41, issue.6, pp.464-467, 1994.

. Amiclaus, Activity: Voltage Level Shifting, p.8, 2019.

P. Allen and &. D. Holberg, CMOS Analog Circuit Design, pp.978-0199937424, 2012.

J. A. Crawford, Frequency synthesizer design handbook, Artech House Microwave Library (Hardcover), 1994.

N. Weste-&-k.-eshraghian, Principles of CMOS VLSI design: a systems perspective, pp.978-0890064405, 1985.

S. Kim, K. Lee, Y. Moon, and D. Jeong, A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL, IEEE Journal of Solid-State Circuits, vol.32, issue.5, pp.691-700, 1997.

H. O. Johansson, A simple precharged CMOS phase frequency detector, IEEE Journal of Solid-State Circuits, vol.33, issue.2, pp.295-299, 1998.

K. P. Thakore, H. M. Parmar-&-n, and . Devashrayee, Low power and low jitter phase frequency detector for phase lock loop, International Journal of Engineering Science and Technology (IJEST), vol.3, 1998.

J. Gupta, A. Sangal, and &. Verma, High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology, World Congress on Information and Communication Technologies, pp.346-349, 2011.

I. A. Young, J. K. Greason-&-k, and . Wong, A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors, IEEE Journal of Solid-State Circuits, vol.27, issue.2, pp.1599-1607, 1992.

R. A. Baki-&-m and . El-gamal, A new CMOS charge pump for low-voltage (1V) high-speed PLL applications, ISCAS, 2003.

H. R. Rategh, H. &. Samavati, and . Lee, A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver, IEEE Journal of Solid-State Circuits, vol.35, issue.5, pp.780-787, 2000.

C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli et al., A family of lowpower truly modular programmable dividers in standard 0.\r35-/spl mu/m CMOS technology, IEEE Journal of Solid-State Circuits, vol.35, issue.7, pp.1039-1045, 2000.

, Hittite Microwave Corporation, Prescalers & Counter Dividers

C. V. Krishna-&-n and . Touba, Reducing test data volume using LFSR reseeding with seed compression, ITC, 2002.

J. L. Massey, Shift-register synthesis and BCH decoding, IEEE Trans. on Information Theory, vol.15, issue.1, pp.122-127, 1969.

A. Klein, Linear Feedback Shift Registers, Stream Ciphers, pp.17-58, 2013.

Y. Leduc, NAPA : Outil de simulation comportementale de systèmes intégrés analogiques et mixtes, 2014.

P. Alfke, Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators, p.7, 1996.

P. E. Allen, Lectures 120 Filters and Charge Pumps, ECE-6440 Frequency Synthesizers, 2003.

F. G. Gardner, Charge-pump phase-lock loops, IEEE Trans. on Communications, issue.11, pp.1849-1858, 1980.

, Online Calculator 2nd / 3rd Order Loopfilter Calculator for PLL, p.1, 2019.

B. Razavi, Design of Analog CMOS Integrated Circuits, pp.978-0072380323, 2000.

C. He, X. Dai, H. Xing, and &. D. Chen, New layout strategies with improved matching performance, Analog Integr. Circuits Signal Process, vol.49, pp.281-289, 2006.

K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers, 2015.

G. Jacquemod, F. Ben-abdeljelil, W. Tatinian, P. Lucchi, M. Borgarino et al., Comparison between RTW VCO and LC QVCO 12 GHz PLLs, Analog Integrated Circuits and Signal Processing, vol.73, pp.749-756, 2012.

Z. Wei, G. Jacquemod, P. Lorenzini, F. Hameau, E. De-foucauld et al., «Study and reduction of variability in 28nm Fully Depleted Silicon on Insulator technology, Journal of Low Power Electronics, vol.12, issue.1, pp.64-73, 2016.

, Conférences Invités

Y. Leduc, Z. Wei, J. Modad, M. A. Garcia-perez, E. De-foucauld et al., «Digital complementary logic in 28 nm FDSOI to address the next nanoelectronic challenges, Nano Science & Technology, p.172, 2015.

G. Jacquemod, E. De-foucauld, Y. Leduc, F. Hameau, Z. Wei et al., 28 nm FDSOI technology using fully complementary inverters, pp.62-64, 2015.

Y. Leduc, G. Jacquemod, Z. Wei, J. Modad, P. Lorenzini et al., «La logique complémentaire, une opportunité offerte par le FDSOI pour l'intégration de circuits mixtes dans les technologies les plus avancées, 2016.

G. Jacquemod, Z. Wei, Y. Leduc, E. De-foucauld, and &. J. Prouvee, Reducing small channel effect of UTBB-FDSOI transistor for current mirror application, ICSS, 2019.

, Conférences Internationales

G. Jacquemod, Z. Wei, J. Modad, E. De-foucauld, F. Hameau et al., Study and reduction of variability in 28 nm FDSOI technology, pp.19-22, 2015.

G. Jacquemod, Z. Wei, P. Lorenzini, and &. Leduc, New Design using UTBB FDSOI Technology, 2016.

G. Jacquemod, Z. Wei, Y. Leduc, and &. Jacquemod, «New QVCO Design using UTBB FDSOI Technology, 2016.

Z. Wei, Y. Leduc, G. Jacquemod, and &. E. De-foucauld, UTBB-FDSOI Complementary Logic for High Quality Analog Signal Processing, pp.572-575, 2016.

Z. Wei, Y. Leduc, E. De-foucauld, and &. G. Jacquemod, «Novel Building Blocks for PLL using Complementary Logic in 28nm UTBB-FDSOI Technology, NewCAS, pp.121-124, 2017.

G. Jacquemod, Z. Wei, Y. Leduc, and &. E. De-foucauld, «Back-gate cross-coupled cells for high performance clock in 28nm FDSOI technology, Nano Science & Technology, 2017.

Z. Wei, G. Jacquemod, J. Prouvee, E. De-foucauld, and &. Y. Leduc, «Low Power IoT Design using FDSOI Technology, SENSO, 2017.

, Conférences Nationales

Z. Wei, Auto-Polarisation de la Grille Arrière pour Auto-Calibration de Cellules Analogiques et Mixtes en Technologie UTBB FDSOI, 2016.

Z. Wei, Y. Leduc, and &. Jacquemod, «Auto-Polarisation de la Grille Arrière pour Auto-Calibration de Cellules Analogiques et Mixtes en Technologie UTBB FDSOI, JNRDM, 2016.

G. Jacquemod, Z. Wei, Y. Leduc, and &. Lorenzini, Application de la technologie FDSOI pour la conception de nouvelles topologies de circuits analogiques et mixtes», Proc. 15ème Journées Pédagogiques du CNFM, 2018.

. Brevets,

P. Audebert, E. De-foucauld, Y. Leduc, G. Jacquemod, Z. Wei et al., Circuit électronique élémentaire pour étage d'amplification ou de recopie de signaux analogiques, 2017.

L. Chapitre-quatre-décrit-l'ensemble-des-blocks-de-base-d'une, P. Vcro, and L. Détecteur-de-phase, Des simulations Spice permettent à chaque fois d'optimiser la taille des transistors et d'évaluer les performances des circuits. Un effort particulier a été apporté à la conception et réalisation de la nouvelle structure du miroir de courant qui permet de limiter les effets de canal court tout en diminuant drastiquement la taille des transistors

, Le dernier chapitre est consacré à la réalisation d'un circuit de test en technologie FDSOI. Nous présentons la réalisation du dessin des masques

, L'ensemble des mesures réalisées est présenté dans ce chapitre et permet de valider le concept de logique complémentaire utilisant le croisement des grilles arrières des transistors UTBB-FDSOI. Les résultats, en termes de performances, sont très prometteurs pour la suite de ce travail

. Enfin, des conclusions générales et quelques perspectives terminent ce manuscrit. Les publications liées à ce travail de thèse sont également présentées

G. Moore, Cramming more components onto integrated circuits, Electronics Magazine, vol.38, issue.8, 1965.

A. Asenov, Device-Circuit Interplay in the Simulation of Statistical CMOS Variability, 2012.

K. Ahmed and &. Schuegraf, Rival architectures face off in a bid to Keep Moore's Law alive, IEEE Spectrum, 2011.

M. Jurczak, N. Collaert, A. Veloso, T. Hoffman, and &. S. Biesemans, Review of FINFET technology, SOI Conference, 2009.

N. Planes, 28nm FDSOI technology platform for high-speed low-digital applications, Digest of technical Papers -Symposium on VLSI Technology, vol.33, pp.133-134, 2012.