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Back-gate feedback for auto-calibration of analog and mixed cells in UTBB-FDSOI technology

Abstract : In the competition of the miniaturization of integrated electronic circuits, UTBB-FDSOI technologies are better adapted to nanometric sizes, because they can limit the problems due to the random doping variations used in conventional “bulk” transistors and bring a significant improvement in terms of performance and low power design. This thesis is a contribution to the development of novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology. Using this technology, we proposed a complementary inverter based on a pair of back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals. This design concept can be extended to any digital cells to generate more stable, symmetrical and resilient output signals. First, we designed a fast and efficient ring oscillator composed by four complementary inverters delivering quadrature clocks which oscillation frequency is 7.3GHz. Then using complementary logic and back-gate control structure, we proposed an efficient solution to produce novel structures of VRCO, PFD, Charge pump, divisor etc., which are the key building blocks of high-speed low noise PLLs. All these designs have been simulated and verified using Cadence. Moreover, a test chip of RO, current mirror and VCRO have already been realized in silicon and tested.
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  • HAL Id : tel-02493990, version 2

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Zhaopeng Wei. Back-gate feedback for auto-calibration of analog and mixed cells in UTBB-FDSOI technology. Micro and nanotechnologies/Microelectronics. Université Côte d'Azur, 2019. English. ⟨NNT : 2019AZUR4033⟩. ⟨tel-02493990v2⟩

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