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Efficient code generation for hardware accelerators by refining partially specified implementation

Ulysse Beaugnon 1, 2
2 Parkas - Parallélisme de Kahn Synchrone
Inria de Paris, DI-ENS - Département d'informatique de l'École normale supérieure, CNRS - Centre National de la Recherche Scientifique
Abstract : Compilers looking for an efficient implementation of a function must find which optimizations are the most beneficial. This is a complex problem, especially in the early steps of the compilation process. Each decision may impact the transformations available in subsequent steps. We propose to represent the compilation process as the progressive refinement of a partially specified implementation. All potential decisions are exposed upfront and commute. This allows for making the most discriminative decisions first and for building a performance model aware of which optimizations may be applied in subsequent steps. We apply this approach to the generation of efficient GPU code for linear algebra and yield performance competitive with hand-tuned libraries.
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https://tel.archives-ouvertes.fr/tel-02385303
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Submitted on : Thursday, November 26, 2020 - 5:50:07 PM
Last modification on : Wednesday, December 2, 2020 - 4:25:12 PM

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Ulysse Beaugnon. Efficient code generation for hardware accelerators by refining partially specified implementation. Programming Languages [cs.PL]. Université Paris sciences et lettres, 2019. English. ⟨NNT : 2019PSLEE050⟩. ⟨tel-02385303v2⟩

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