, Avantage des VTPRs par rapport à l'utilisation d'une fréquence pessimiste

, Comparaison avec une implémentation native depuis les sources136

.. .. Résumé,

. .. Le-cadre-cloud,

.. .. Exigences,

.. .. Solutions,

. .. Contrôle,

. .. Modèle-de-coût, 164 6.6.1 Modélisation des temps de sauvegarde et de restauration

.. .. Résumé,

P. Figuli, M. Hübner, R. Girardey, F. Bapp, T. Bruckschlögl et al., A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion, Adaptive Hardware and Systems (Ahs), 2011 Nasa/esa Conference on, pp.96-103, 2011.

J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, Internet of Things (IoT) : A vision, architectural elements, and future directions, Future generation computer systems, vol.29, issue.7, pp.1645-1660, 2013.

. Saurabh-kumar-garg, K. Srinivasa, R. Gopalaiyengar, and . Buyya, SLA-based resource provisioning for heterogeneous workloads in a virtualized cloud datacenter, International conference on Algorithms and architectures for parallel processing, pp.371-384, 2011.

D. John, M. Owens, D. Houston, S. Luebke, J. E. Green et al., GPU computing. Proceedings of the IEEE, vol.96, pp.879-899, 2008.

E. John, D. Stone, G. Gohara, and . Shi, OpenCL : A parallel programming standard for heterogeneous computing systems, Computing in science & engineering, vol.12, issue.3, pp.66-73, 2010.

T. Vignesh, M. Ravi, G. Becchi, S. Agrawal, and . Chakradhar, Supporting GPU sharing in cloud environments with a transparent runtime consolidation framework, Proceedings of the 20th international symposium on High performance distributed computing, pp.217-228, 2011.

M. Smith, Application-specific integrated circuits, 2008.

D. Stephen, . Brown, J. Robert, J. Francis, Z. Rose et al., Field-programmable gate arrays, vol.180, 2012.

J. Cong, B. Liu, S. Neuendorffer, and J. Noguera, High-level synthesis for FPGAs : From prototyping to deployment, Kees Vissers, and Zhiru Zhang, vol.30, pp.473-491, 2011.

W. Lie and W. Feng-yan, Dynamic partial reconfiguration in FPGAs, Intelligent Information Technology Application, vol.2, pp.445-448, 2009.

. Xilinx, Acceleration in the AWS Cloud

A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides et al., A reconfigurable fabric for accelerating large-scale datacenter services, Computer Architecture (ISCA), 2014.

, ACM/IEEE 41st International Symposium on, pp.13-24, 2014.

T. Prickett-morgan, Why Hyperscalers And Clouds Are Pushing Intel Into FPGAs, 2015.

W. Fornaciari and V. Piuri, Virtual FPGAs : Some steps behind the physical barriers, Parallel and Distributed Processing, pp.7-12, 1998.

W. Fornaciari, V. Piuri, and L. Ripamonti, Virtualization of FPGA via Segmentation, FPGA, p.222, 2000.

H. Simmler, L. Levinson, and R. Männer, Multitasking on FPGA coprocessors, International Workshop on Field Programmable Logic and Applications, pp.121-130, 2000.

H. Walder and M. Platzner, Reconfigurable Hardware Operating Systems : From Design Concepts to Realizations, Engineering of Reconfigurable Systems and Algorithms, pp.284-287, 2003.

O. Diessel, H. Elgindy, M. Middendorf, H. Schmeck, and B. Schmidt, Dynamic scheduling of tasks on partially reconfigurable FP-GAs, IEE Proceedings-Computers and Digital Techniques, vol.147, issue.3, pp.181-188, 2000.

H. Kalte and M. Porrmann, Context saving and restoring for multitasking in reconfigurable systems, Field Programmable Logic and Applications, 2005. International Conference on, pp.223-228, 2005.

A. Bourge, O. Muller, and F. Rousseau, Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.10, issue.1, p.9, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01367798

L. Lagadec, D. Lavenier, E. Fabiani, and B. Pottier, Placing, routing, and editing virtual FPGAs, FPL, vol.1, pp.357-366
URL : https://hal.archives-ouvertes.fr/hal-02013412

. Springer, , 2001.

R. Kirchgessner, G. Stitt, A. George, and H. Lam, VirtualRC : a virtual FPGA platform for applications and tools portability, Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, pp.205-208, 2012.

A. Brant, G. F. Guy, and . Lemieux, ZUMA : An open FPGA overlay architecture, Field-Programmable Custom Computing Machines (FCCM), pp.93-96, 2012.

J. Coole and G. Stitt, Intermediate fabrics : Virtual architectures for circuit portability and fast placement and routing, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp.13-22, 2010.

G. Stitt and J. Coole, Intermediate fabrics : Virtual architectures for near-instant fpga compilation, IEEE Embedded Systems Letters, vol.3, issue.3, pp.81-84, 2011.

I. Lebedev, S. Cheng, A. Doupnik, J. Martin, C. Fletcher et al., MARC : A many-core approach to reconfigurable computing, Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on, pp.7-12, 2010.

D. Picard, Méthodes et outils logiciels pour l'exploration architecturale d'unités reconfigurables embarquées, 2010.

L. Sekanina and . Richard, Design of the Special Fast Reconfigurable Chip Using Common FPGA, In : Proc. of the Design and Diagnostic of Electronic Circuits and Systems IEEE DDECS'2000, Polygrafia SAF. Citeseer, 2000.

A. Dehon, DPGA utilization and application, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, pp.115-121, 1996.

K. Roman-l-lysecky and . Miller, Frank Vahid, and Kees A Vissers. Firm-core virtual FPGA for just-in-time FPGA compilation, FPGA, p.271, 2005.

R. Lysecky, F. Vahid, and S. Tan, Dynamic FPGA routing for just-in-time FPGA compilation, Proceedings of the 41st annual Design Automation Conference, pp.954-959, 2004.

A. Brant, Coarse and fine grain programmable overlay architectures for FPGAs, 2013.

D. Koch, C. Beckhoff, . Guy, and . Lemieux, An efficient FPGA overlay for portable custom instruction set extensions, Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on, pp.1-8, 2013.

D. Capalija and . Tarek-s-abdelrahman, A high-performance overlay architecture for pipelined execution of data flow graphs, Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on, pp.1-8, 2013.

A. Severance, G. F. Guy, and . Lemieux, Embedded supercomputing in FP-GAs with the VectorBlox MXP matrix processor, Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2013 International Conference on, pp.1-10, 2013.

A. Kumar-jain, D. L. Maskell, . Suhaib, and . Fahmy, Are coarsegrained overlays ready for general purpose application acceleration on FP-GAs ?, Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress, pp.586-593, 2016.

C. Liu, H. Ng, and H. So, QuickDough : a rapid fpga loop accelerator design framework using soft CGRA overlay, Field Programmable Technology (FPT), 2015 International Conference on, pp.56-63, 2015.

S. Shukla, W. Neil, J. Bergmann, and . Becker, Quku : A two-level reconfigurable architecture, Emerging VLSI Technologies and Architectures, p.6, 2006.

A. Kumar-jain, A. Suhaib, D. Fahmy, and . Maskell, Efficient Overlay architecture based on DSP blocks, Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, pp.25-28, 2015.

L. Hao and G. Stitt, Virtual finite-state-machine architectures for fast compilation and portability, Application-Specific Systems, Architectures and Processors (ASAP), pp.91-94, 2013.

P. Cooke, L. Hao, and G. Stitt, Finite-state-machine overlay architectures for fast FPGA compilation and application portability, ACM Transactions on Embedded Computing Systems (TECS), vol.14, issue.3, p.54, 2015.

J. Coole and G. Stitt, Adjustable-cost overlays for runtime compilation, Field-Programmable Custom Computing Machines (FCCM), 2015.

, IEEE 23rd Annual International Symposium on, pp.21-24, 2015.

V. Betz and J. Rose, VPR : A new packing, placement and routing tool for FPGA research, International Workshop on Field Programmable Logic and Applications, pp.213-222, 1997.

V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for deep-submicron FPGAs, vol.497, 2012.

V. Betz and J. Rose, Automatic generation of FPGA routing architectures from high-level descriptions, Proceedings of the 2000 ACM/-SIGDA eighth international symposium on Field programmable gate arrays, pp.175-184, 2000.

L. Lagadec, Abstraction, modélisation et outils de CAO pour les architectures réconfigurables, 2000.

L. Lagadec and B. Pottier, Object-oriented meta tools for reconfigurable architectures, Reconfigurable Technology : FPGAs for Computing and Applications II, vol.4212, pp.69-80, 2000.
URL : https://hal.archives-ouvertes.fr/hal-02133775

L. Lagadec, C. Teodorov, J. Le-lann, D. Picard, and E. Fabiani, Model-driven toolset for embedded reconfigurable cores : Flexible prototyping and software-like debugging, Science of Computer Programming, vol.96, pp.156-174, 2014.
URL : https://hal.archives-ouvertes.fr/hal-00998533

B. D. Sutter, P. Raghavan, and A. Lambrechts, Coarse-grained reconfigurable array architectures, Handbook of signal processing systems, pp.553-592, 2013.

X. Yue, Rapid Overlay Builder for Xilinx FPGAs, 2014.

T. Wiersema, A. Bockhorn, and M. Platzner, Embedding FPGA overlays into configurable systems-on-chip : ReconOS meets ZUMA, Re-ConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on, pp.1-6, 2014.

M. Hubner, P. Figuli, R. Girardey, D. Soudris, K. Siozios et al., A heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture, Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on, pp.143-149, 2011.

A. Agne, M. Happe, A. Keller, E. Lubbers, B. Plattner et al., ReconOS : An operating system approach for reconfigurable computing, IEEE Micro, vol.34, issue.1, pp.60-71, 2014.

E. Lübbers and M. Platzner, ReconOS : Multithreaded programming for reconfigurable computers, ACM Transactions on Embedded Computing Systems (TECS), vol.9, issue.1, 2009.

F. Chen, Y. Shan, Y. Zhang, Y. Wang, H. Franke et al., Enabling FPGAs in the cloud, Proceedings of the 11th ACM Conference on Computing Frontiers, 2014.

, OpenStack is open source software for creating private and public clouds

S. Byma, G. Steffan, H. Bannazadeh, A. L. Garcia, and P. Chow, Fpgas in the cloud : Booting virtualized hardware accelerators with openstack, Field-Programmable Custom Computing Machines (FCCM), pp.109-116, 2014.

T. Bollengier, L. Lagadec, J. Le-lann, and P. Guilloux, Soft Timing Closure for Soft Programmable Logic Cores : The AR-Gen Approach, Applied Reconfigurable Computing : 13th International Symposium, vol.10216, p.93, 2017.

M. Gordon, J. Hurd, and K. Slind, Executing the formal semantics of the accellera property specification language by mechanised theorem proving, CHARME, pp.200-215, 2003.

M. Boulé and Z. Zilic, Efficient automata-based assertion-checker synthesis of PSL properties, High-Level Design Validation and Test Workshop, pp.69-76, 2006.

, Specification for the WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores, 2002.

, Armadeus. L'APF6_SP pour les systèmes Linux embarqués

L. Lagadec, J. Le-lann, and T. Bollengier, A prototyping platform for virtual reconfigurable units, 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, pp.1-7, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01006128

, Texas Instruments. AN-1469 PHYTER Design & Layout Guide, 2006.

, OpenCores

. Zylin and . Zylin, , 2008.

, Motorola Inc. SPI Block Guide V03.06, 2000.

S. Bourdeauducq, Minimac -the minimalist Ethernet MAC, 2010.

, FreeRTOS -Market leading RTOS (Real Time Operating System) for embedded systems with Internet of Things extensions

. Chan, FatFs -Generic FAT File System Module, 2017.

A. Dunkels, Design and Implementation of the lwIP TCP/IP Stack. Swedish Institute of Computer Science, vol.2, p.77, 2001.

, Altera. Avalon Interface Specifications

T. Gingold and . Ghdl, A VHDL compiler, 2007.

F. Martinolle and A. Sherer, A procedural language interface for VHDL and its typical applications, Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings, pp.32-38, 1998.

C. Pilato and F. Ferrandi, Bambu : A Free Framework for the High-Level Synthesis of Complex Applications, 2012.

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona et al., Le-gUp : high-level synthesis for FPGA-based processor/accelerator systems, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, pp.33-36, 2011.

, Berkeley Logic Interchange Format (BLIF), 1992.

. Edif-steering-committee, EDIF Electronic Design Interchange Format Version 2 0 0. Electronic Industries Association, 1987.

P. Jamieson, B. Kenneth, F. Kent, L. Gharibian, and . Shannon, Odin ii-an open-source verilog hdl synthesis tool for cad research, Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on, pp.149-156, 2010.

P. Bellows and B. Hutchings, JHDL-an HDL for reconfigurable systems, FPGAs for Custom Computing Machines, pp.175-184, 1998.

N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas et al., Torc : towards an open-source tool flow, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, pp.41-44, 2011.

C. Beckhoff, D. Koch, and J. Torresen, The xilinx design language (xdl) : Tutorial and use cases, Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on, pp.1-8, 2011.

, ABC : A system for sequential synthesis and verification, 2013.

A. Mishchenko, S. Chatterjee, and R. Brayton, DAG-aware AIG rewriting : A fresh look at combinational logic synthesis, Design Automation Conference, 2006 43rd ACM/IEEE, pp.532-535, 2006.

R. Brayton and A. Mishchenko, ABC : An academic industrialstrength verification tool, International Conference on Computer Aided Verification, pp.24-40, 2010.

M. Ellen, K. Sentovich, L. Singh, C. Lavagno, R. Moon et al., SIS : A system for sequential circuit synthesis, 1992.

N. Shenoy and R. Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computeraided design, pp.226-233, 1994.

M. Graphics, A. Modelsim, and F. Design,

S. Williams, Icarus Verilog

, IEEE Design Automation Sub-Committee et al. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, 1996.

J. Rose, J. Luu, C. W. Yu, O. Densmore, J. Goeders et al., The VTR project : architecture and CAD for FPGAs from verilog to routing, Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, pp.77-86, 2012.

. Lukas-ppp-van-ginneken, Buffer placement in distributed RC-tree networks for minimal Elmore delay, IEEE International Symposium on, pp.865-868, 1990.

J. E. Steven, N. Wilton, . Kafafi, C. H. James, K. A. Wu et al., Design considerations for soft embedded programmable logic cores, IEEE Journal of Solid-State Circuits, vol.40, issue.2, pp.485-497, 2005.

&. Vc-aken, G. Ova, R. Lemieux, and . Saleh, An improved" soft" eFPGA design and implementation strategy, Custom Integrated Circuits Conference, pp.179-182, 2005.

N. Weaver, Y. Markovskiy, Y. Patel, and J. Wawrzynek, Postplacement C-slow retiming for the Xilinx Virtex FPGA, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, pp.185-194, 2003.

, Altera. AN715 Hyper-Pipelining for Stratix 10 Designs, 2015.

K. Eguro and S. Hauck, Armada : timing-driven pipeline-aware routing for FPGAs, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, pp.169-178, 2006.

L. Mcmurchie and C. Ebeling, PathFinder : a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp.111-117, 1995.

I. Kuon and J. Rose, Measuring the gap between FPGAs and ASICs, IEEE Transactions on computer-aided design of integrated circuits and systems, vol.26, issue.2, pp.203-215, 2007.

P. Mell and T. Grance, The NIST definition of cloud computing. National Institute of Standards and Technology, vol.53, p.50, 2009.

P. Patel, H. Ajith, A. Ranabahu, and . Sheth, Service level agreement in cloud computing, 2009.

T. Vignesh, M. Ravi, G. Becchi, S. T. Agrawal, and . Chakradhar, Supporting GPU sharing in cloud environments with a transparent runtime consolidation framework, Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, HPDC 2011, pp.217-228, 2011.

S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach, Accelerating compute-intensive applications with GPUs and FPGAs, Application Specific Processors, pp.101-107, 2008.

A. Madhavapeddy and S. Singh, Reconfigurable data processing for clouds, Field-Programmable Custom Computing Machines (FCCM), 2011.

, IEEE 19th Annual International Symposium on, pp.141-145, 2011.

A. Putnam, E. Caulfield, D. Chung, K. Chiou, J. Constantinides et al., A reconfigurable fabric for accelerating large-scale datacenter services, Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pp.13-24, 2014.

S. Asano, T. Maruyama, and Y. Yamaguchi, Performance comparison of FPGA, GPU and CPU in image processing, Field Programmable Logic and Applications, pp.126-131, 2009.

J. Scaramella, M. Marden, J. Daly, and R. Perry, The Cost of Retaining Aging IT Infrastructure, pp.2017-2019, 2014.

C. Tiago, . Ferreto, A. S. Marco, R. N. Netto, C. Calheiros et al., Server consolidation with migration control for virtualized data centers, Future Generation Computer Systems, vol.27, issue.8, pp.1027-1034, 2011.

I. Nidhi-jain-kansal and . Chana, Cloud load balancing techniques : A step towards green computing, IJCSI International Journal of Computer Science Issues, vol.9, issue.1, pp.238-246, 2012.

A. Suhaib, K. Fahmy, S. Vipin, and . Shreejith, Virtualized FPGA accelerators for efficient cloud computing, Cloud Computing Technology and Science (CloudCom), pp.430-435, 2015.

J. Weerasinghe and R. Polig, Francois Abel, and Christoph Hagleitner. Network-Attached FPGAs for Data Center Applications, 2016.

A. Bourge, Changement de contexte matériel sur FPGA entre équipements reconfigurables et hétérogènes dans un envirtonnement de calcul distribué, 2016.

A. Kumar-jain, D. L. Maskell, . Suhaib, and . Fahmy, Throughput oriented FPGA overlays using DSP blocks, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1628-1633, 2016.

M. Najem, T. Bollengier, J. Le-lann, and L. Lagadec, Extended Overlay Architectures For Heterogeneous FPGA Cluster Management, Journal of Systems Architecture, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01643297

M. Najem, T. Bollengier, J. Le-lann, and L. Lagadec, A cost-effective approach for efficient time-sharing of reconfigurable architectures, FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC, pp.7-12, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01656613

T. Bollengier, M. Najem, J. Le-lann, and L. Lagadec, Demo : Overlay architectures for heterogeneous FPGA cluster management, Design and Architectures for Signal and Image Processing (DASIP), 2016 Conference on, pp.239-240, 2016.

T. Bollengier, M. Najem, J. Le-lann, and L. Lagadec, Zeff : Une plateforme pour l'intégration d'architectures overlay dans le cloud, COMPAS 2016, 2016.

T. Bollengier, M. Najem, J. Le-lann, and L. Lagadec, Overlay architectures for fpga resource virtualization, GDR SOC SIP, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01405912

N. Mohamad, B. Théotime, L. Le-jean-christophe, and . Lagadec, Fpgas in the cloud : a hybrid hadrware/software framework, 2016.

D. Dickin and L. Shannon, Exploring FPGA technology mapping for fracturable LUT minimization, Field-Programmable Technology (FPT), 2011 International Conference on, pp.1-8, 2011.