Cryogenic electronics and quantum dots on silicon-on-insulator for quantum computing

Abstract : This thesis studies cryogenic electronics and quantum dots on silicon-on-insulator (SOI) for quantum computing. Different types of electron and hole quantum dots are fabricated with Leti's SOI nanowire (NW) and planar 28nm FD-SOI technology. In the first part, Pauli Spin Blockade (PSB) is studied for the first holes down to 60mK. We show that it is governed by a strong spin orbit coupling (SOC). The intradot relaxation rate of 120kHz was found for the first holes. The access barriers tunability realized with additional gates was proven to be efficient regarding the isolation of qubit from source/drain metallic leads. Following the recent demonstration of electron-dipole spin resonance (EDSR) achieved in electron quantum dots confined in the corners of silicon nanowire (CDs), we deeply investigated quantum dots in several multi-gate samples under different body-biasing conditions. Based on preliminary cryogenic transport measurements, an operation protocol for a compact two electron spin qubit gate has been proposed.Regarding cryogenic electronics required for an efficient control, manipulation and read-out of a large number of qubits, the low temperature digital and analog performance of 28nm FD-SOI MOSFETs was analysed from room temperature down to 4K. Significant improvements in transistor performance are achieved with a clear enhancement of carrier mobility and a strong reduction of subthreshold swing (SS), even for short-channel devices with gate length down to 28nm. The saturation of the subthreshold swing at low temperature is explained with a new analytical model developed in this thesis. By introducing a narrow tail in the density of states at the edges of the conduction and valence bands and using the Fermi-Dirac statistics, an excellent agreement of SS is achieved between experiments and modelling. The analysis of the SS-IDS metric under different forward body-biasing (FBB) conditions has revealed that the increased density of interface traps cannot be responsible for the SS saturation at low temperature. By adding a slight exponential variation in the interface trap density, we show that the SS-IDS curve can be well reproduced over more than 6 decades, paving a way for an efficient cryogenic design of CryoCMOS.In a second time, cryogenic performance of Ring Oscillators (RO) down to 4K was investigated. We have shown that the optimal supply voltage can be reduced down to 0.3V. This allows to efficiently reduce the dynamic and static power dissipations. At the same time, a small Energy-Delay product of 6.9fJ.ps with a delay per stage of 37ps were achieved at VDD=0.325V under aggressive FBB.Finally, in the last chapter, the duality of short-channel FD-SOI transistors operation as FETs or SETs is demonstrated at 4K. By benchmarking the QDs with respect to the common silicon platforms, we show that 28nm FD-SOI technology has a great potential for both cryogenic electronics and qubits.
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Heorhii Bohuslavskyi. Cryogenic electronics and quantum dots on silicon-on-insulator for quantum computing. Quantum Physics [quant-ph]. Université Grenoble Alpes, 2018. English. ⟨NNT : 2018GREAY080⟩. ⟨tel-02183484⟩

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