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, Scaling of the proposed approach

, Per cycle AVF for VEX processor

, Error occurrences per storage structure for the matrix multiplication (Normalized), p.61

. .. , Hardware components inserted in the VLIW pipeline, p.67

. .. , Simulation tool flow for performance evaluation results, p.68

, 5 permanent errors, p.69

, VLIW enhanced with the proposed mechanism

, Illustration example of the proposed mechanism

, Components of complex FU enhanced with BICS

.. .. Control,

, Proposed mechanism performance for fft benchmark under different number of faults and fault duration

, List of Tables 1.1 VEX Compiled Applications' Profiling

, Bit composition for the used VLIW architecture

, Area of pipeline stages (µm 2 )

, Logical masking for three logic gates

, Per stage IVF for all operations of the

, ID encoding in the information extraction unit

, ) for different n-issue configurations

, Area footprint and power estimation results

. .. , Area and power overhead to the unprotected approach, vol.56

, Per stage IVF for all operations of the

, DMR (TMR) performance overhead (%) for the proposed approach with respect to DMR (TMR) without faults

, 2 Performance gain (%) estimation of the proposed approach over existing approaches for multiple permanent errors

, Performance comparison (execution cycles) under several multiple faults and average performance overhead (%)

M. Min, Step) for each group

A. Footprint and .. .. Power-estimation,