Skip to Main content Skip to Navigation
Theses

Contribution to the study of the SiC MOSFETs gate oxide

Abstract : SiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate.
Document type :
Theses
Complete list of metadata

Cited literature [197 references]  Display  Hide  Download

https://tel.archives-ouvertes.fr/tel-02124585
Contributor : Abes Star :  Contact
Submitted on : Thursday, May 9, 2019 - 4:46:08 PM
Last modification on : Monday, September 13, 2021 - 2:44:04 PM

File

these.pdf
Version validated by the jury (STAR)

Identifiers

  • HAL Id : tel-02124585, version 1

Citation

Oriol Aviñó Salvadó. Contribution to the study of the SiC MOSFETs gate oxide. Electronics. Université de Lyon, 2018. English. ⟨NNT : 2018LYSEI110⟩. ⟨tel-02124585⟩

Share

Metrics

Record views

253

Files downloads

2070