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, Example of public-key cryptography usage in the EDA tool for a secure key exchange and IP block transmission (adapted from [Gua+09]), p.53
, MA) in the transactions between an FPGA vendor (FV), a system integrator (SYS) and two IP core designers (CV) (from [MSV12])
, Overview of the IP protection module designed in the framework of the SAL-WARE project
, 2 Two examples of logic functions and the inputs that can lock their output, p.64
, Propagation of a locking value through a sequence of nodes (in thick red), p.65
, Deletion of the incoming edges of vertices that do not satisfy forced ? locks and removal of connected components that do not contain any output, p.67
, Diierent types of connected components that are found in the nal graph. The node(s) select to be modiied for logic locking are highlighted in orange, p.68
, 69 2.8 Original and locked vertices depending on the associated activation bit, p.70
, Locking vertices and edges added to the graph
, Area overhead as the percentage of extra logic gates required to implement logic locking
, Computation time required to process a netlist for logic locking and for fault analysis-based logic masking
, 77 2.16 OR locking gate (in dark grey) obfuscated by two extra gates (in light grey) with logic values shown in red, vol.79
, 91 AND gate (a) or three 2-input AND gates (b). The resulting graphs (c) and (d) lead to diierent degree centrality values for the vertex 5, Degree centrality values for the vertices of a random graph
, Closeness centrality values for the vertices of a random graph, p.92
, Betweenness centrality values for the vertices of a random graph, p.93
, 94 obtained for several logic resources overhead
, Computation time required for the centrality indicators considered for diierent benchmark sizes
, 102 3.11 Graph for which selecting the vertices with the highest centrality does not alter the outputs optimally, Trade-oo between masking eeciency and computation time for diierent node selection heuristics at 5% logic resources overhead
, Illustration of the similarities between key reconciliation and reliable shared key generation from a PUF response
, CONFIRM applied on 16-bit blocks
, 114 of executing the CASCADE protocol on 16-bit responses with ve errors
, Implementation of the parity computation module when the response is stored in RAM
, Leakage values (in bits) obtained with diierent error rates, initial block sizes and number of passes
, Failure rate values obtained with diierent error rates, initial block sizes and number of passes
, Changes in the number of bits in the response at diierent steps, p.135
, Module de protection des données de conception
, Part of the design ow augmented for logic locking or logic masking, p.140
, 149 5.10 HECTOR board management tab of the graphical user interface, p.150
, Enrolment tab of the graphical user interface
, Activation tab of the graphical user interface
, Graphical user interface to the hardware multiplier with input 500×2, p.151
, Graphical user interface to the hardware multiplier with input 25×4, p.151
, Simpliied design ow with steps implementing secure remote activation highlighted
, 16 Example of the c2670 benchmark, which comprises 1117 logic gates, converted into a directed acyclic graph, vol.183, p.189
, 184 18 Example of connected components found in the nal graph after analysis for combinational logic locking
, Logic resources required by the presented error-correction schemes on FPGA, p.39
, Masking eeciency opposed to computational complexity for existing nodes selection heuristics. The symbol × means that the property is not fulllled, the symbol ? means that the property is fulllled
, Knowledge of the keys and encrypted data among parties (?: known, ×: unknown)
, Association of solutions to achieve complete IP protection, p.56
, Suitability of IP protection solutions at addressing diierent threats, p.56
, Controlling value of non-linear logic gates and the associated forced output value 62 2.2 forced and locks values for the internal nodes of the netlist in Figure 2.4a, p.67
, Experimental results obtained when applying combinational logic locking on ITC'99 benchmarks
, Logic resources required to implement a hardware point function for diierent input and output widths
, Contingency table of the binary variables y[i] and y masked, p.86
, Masking eeciency evaluation by diierent metrics. ? stands for the masking eeciency being evaluated as good by the metric. × stands for the masking eeciency being evaluated as bad by the metric, vol.87
, Their logic equation is of the form = (() if is a unary boolean function or = (, ) if is a binary boolean function, Controllability values of the output of usual 1 and 2-input logic gates
, Observability values of the input(s) of usual 1 and 2-input logic gates, p.89
, 97 results obtained when applying logic masking on ITC'99 and EPFL benchmarks for diierent centrality indicators
, Experimental results obtained when applying logic masking on ITC'99 and EPFL benchmarks for diierent centrality indicators
, Distance from the inserted logic masking gates to the inputs/outputs when using diierent centrality indicators
, Block sizes used for the rst passes and after
, 2 Examples of parameters to achieve failure-rates of 10 ?4 , 10 ?6 and 10 ?8 for diierent PUF architectures, aiming at keeping at least 128 bits secret, p.121
, Distribution of operations between device and server, p.122
, Leakage values (in bits) obtained with diierent error rates, initial block sizes and number of passes
, Order of magnitude of the failure rate values obtained with diierent error rates, initial block sizes and number of passes
, Logic resources required for three implementation options of the parity computation module and three response sizes
, Device-side execution time in clock cycles of diierent codes with diierent constructions
, Logic resources required to implement a lightweight block cipher (from
,
, Logic resources required to implement the AW decoder
, Device-side implementation results for the whole design data protection module 148