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Modélisation et gestion du trafic dans le cadre de réseaux sur puce multi-FPGA

Abstract : With the increasing complexity of System-on-Chip, the design of efficient embedded systems dedicated for multimedia applications must integrate effective communication interconnects such as Network-on-Chip. Given the limited number of resources of a single FPGA, multi-FPGA platforms are considered the most appropriate means for experimentation, emulation and evaluation for such large systems. Deployment often involves partitioning the Network-on-Chip on several FPGA and replacing internal communication links with external ones. The limitation of this solution stems from the fact that with ongoing evolution of FPGAs, their I/O resources become scarcer in time. This, consequently, decreases intra-FPGA bandwidth. Currently, the number of inter-FPGA signals is considered a major problem to prototype a Network-on-Chip on multi-FPGA. Since there are more signals needed for routers than the number of available FPGA I/Os. Therefore, inter-FPGA links must be shared between routers, resulting in significant bottlenecks. Since the ratio of logical capacity to the number of IOs increases slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs.The main contributions of this thesis are : (1). We have developed two collision management architectures, one is based on a random access (Backoff) and the other is based on a round-robin algorithm. Timing and resources comparisons are made to evaluate the two inter-FPGA traffic management architectures. The Backoff-based sub-NoC architecture effectively shares external links between multiple routers with a minimum number of collision and balances access between all routers. The new inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions such as Round-Robin and Hierarchical Round-Robin Arbiter. (2) A modeling methodology has emerged to estimate the number of resources used by each architecture. This modeling is based on linear regression. There are considerable over-estimations in the round-robin compared to the Backoff. (3) A NoC architecture dedicated for multimedia applications has been proposed. The objective of such architecture is to transmit traffic with different priority levels under right conditions. In this architecture of NoC multimedia, we have doubled the physical links instead of using virtual channels to allow high priority traffic to recover the delay and to ensure quality of service. In Additionally we have integrated within the routers a simple arbiter to deal with the priority levels for each packet. This new architecture has been compared with traditional architecture based on virtual channels using several test partitioning. Finally, an analytical study was proposed to estimate the number of APs needed for the NoC Multimedia deployed in multi-FPGA systemse to meet the user’s requirements
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Submitted on : Thursday, April 18, 2019 - 9:44:06 AM
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  • HAL Id : tel-02103089, version 1


Atef Dorai. Modélisation et gestion du trafic dans le cadre de réseaux sur puce multi-FPGA. Micro et nanotechnologies/Microélectronique. Université de Lyon; Université de Monastir (Tunisie), 2017. Français. ⟨NNT : 2017LYSES018⟩. ⟨tel-02103089⟩



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