S. Abbaspour, F. Brandner, and M. Schoeberl, A time-predictable stack cache, Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), pp.1-8, 2013.
URL : https://hal.archives-ouvertes.fr/hal-01108105

B. Akesson, K. Goossens, and M. Ringhofer, Predator: a predictable SDRAM memory controller, Hardware/Software Codesign and System Synthesis (CODES+ ISSS), pp.251-256, 2007.

M. Alras, P. Caspi, A. Girault, R. , and P. , Model-based design of embedded control systems by means of a synchronous intermediate model, Embedded Software and Systems, 2009. ICESS'09. International Conference on, pp.3-10, 2009.

E. Amaldi, S. Coniglio, L. G. Gianoli, and C. U. Ileri, On single-path network routing subject to max-min fair flow allocation, Electronic Notes in Discrete Mathematics, vol.41, pp.543-550, 2013.

H. Ayed, J. Ermont, J. Scharbarg, and C. Fraboul, Towards a unified approach for worst-case analysis of tilera-like and kalray-like noc architectures, Factory Communication Systems (WFCS), pp.1-4, 2016.
URL : https://hal.archives-ouvertes.fr/hal-02001640

J. Bahn and N. Bagherzadeh, A generic traffic model for on-chip interconnection networks, p.22, 2009.

P. Bahrebar and D. Stroobandt, The Hamiltonian-based odd-even turn model for maximally adaptive routing in 2D mesh networks-on-chip, Computers & Electrical Engineering, vol.45, pp.386-401, 2015.

C. Ballabriga, H. Cassé, C. Rochange, and P. Sainrat, OTAWA: An open toolbox for adaptive WCET analysis, SEUS 2010, pp.35-46, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01055378

R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, and P. Marwedel, Scratchpad memory: a design alternative for cache on-chip memory in embedded systems, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES, pp.73-78, 2002.

M. Becker, D. Dasari, B. Nicolic, B. Åkesson, V. Nélis et al., Contention-free execution of automotive applications on a clustered many-core platform, 28th Euromicro Conference on Real-Time Systems (ECRTS), pp.14-24, 2016.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce et al., Tile64-processor: A 64-core soc with mesh interconnect, Solid-State Circuits Conference, pp.88-598, 2008.

L. Benini and G. De-micheli, Networks on chip: a new paradigm for systems on chip design, Design, Automation and Test in Europe Conference and Exhibition, pp.418-419, 2002.

A. Benveniste and G. Berry, The synchronous approach to reactive and real-time systems, Proceedings of the IEEE, vol.79, issue.9, pp.1270-1282, 1991.
URL : https://hal.archives-ouvertes.fr/inria-00075115

C. Berg, Plru cache domino effects, OASIcs-OpenAccess Series in Informatics, vol.4, 2006.

G. Berry, SCADE: Synchronous design and validation of embedded control software, Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems, pp.19-33, 2007.

G. Berry and L. Cosserat, The ESTEREL synchronous programming language and its mathematical semantics, International Conference on Concurrency, pp.389-448, 1984.
URL : https://hal.archives-ouvertes.fr/inria-00076230

D. P. Bertsekas, R. G. Gallager, and P. Humblet, Data networks, vol.2, pp.493-536, 1992.

G. B. Bezerra, S. Forrest, M. Moses, A. Davis, and P. Zarkesh-ha, Modeling NoC traffic locality and energy consumption with rent's communication probability distribution, Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, pp.3-8, 2010.

R. V. Boppana, S. Chalasani, and C. Raghavendra, Resource deadlocks and performance of wormhole multicast routing algorithms, IEEE Transactions on Parallel and Distributed Systems, vol.9, issue.6, pp.535-549, 1998.

A. Bouillard and G. Stea, Worst-Case Analysis of Tandem Queueing Systems Using Network Calculus, Quantitative Assessments of Distributed Systems: Methodologies and Techniques, pp.129-173, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01272090

M. Boyer, B. Dupont-de-dinechin, A. Graillat, and L. Havet, Computing routes and delay bounds for the network-on-chip of the kalray mppa2 processor, ERTS 2018-9th European Congress on Embedded Real Time Software and Systems, 2018.
URL : https://hal.archives-ouvertes.fr/hal-01707911

M. Boyer, J. Migge, and N. Navet, An efficient and simple class of functions to model arrival curve of packetised flows, Proceedings of the 1st International Workshop on Worst-Case Traversal Time, pp.43-50, 2011.

M. Boyer, N. Navet, and M. Fumey, Experimental assessment of timing verification techniques for afdx, 6th European Congress on Embedded Real Time Software and Systems, 2012.
URL : https://hal.archives-ouvertes.fr/hal-01345472

M. Boyer, G. Stea, and W. M. Sofack, Deficit round robin with network calculus, Performance Evaluation Methodologies and Tools (VALUETOOLS), 2012 6th International Conference on, pp.138-147, 2012.

G. Breaban, S. Stuijk, and K. Goossens, Efficient synchronization methods for let-based applications on a multi-processor system on chip, 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1721-1726, 2017.

T. Carle, M. Djemal, D. Potop-butucaru, R. De-simone, and Z. Zhang, Static mapping of real-time applications onto massively parallel processor arrays, Application of Concurrency to System Design (ACSD), pp.112-121, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01095130

T. Carle, D. Potop-butucaru, Y. Sorel, and D. Lesens, From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation, Leibniz Transactions on Embedded Systems(LITES), vol.2, issue.2, pp.1-1, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01263994

P. Caspi, A. Curic, A. Maignan, C. Sofronis, S. Tripakis et al., From Simulink to SCADE/Lustre to TTA: a layered approach for distributed embedded applications, ACM Sigplan Notices, pp.153-162, 2003.

P. Caspi, A. Girault, and D. Pilaud, Automatic distribution of reactive systems for asynchronous networks of processors, IEEE T Software Engineering, vol.25, issue.3, pp.416-427, 1999.
URL : https://hal.archives-ouvertes.fr/inria-00073196

P. Caspi, N. Scaife, C. Sofronis, and S. Tripakis, Semantics-preserving multitask implementation of synchronous programs, ACM Transactions on Embedded Computing Systems (TECS), vol.7, issue.2, p.15, 2008.

A. Champion, A. Mebsout, C. Sticksel, and C. Tinelli, The Kind 2 model checker, International Conference on Computer Aided Verification, pp.510-517, 2016.

R. N. Charette, This car runs on code, IEEE spectrum, vol.46, issue.3, p.3, 2009.

S. Chen and K. Nahrstedt, Maxmin fair routing in connection-oriented networks, Proc. Euro-Parallel and Distributed Systems Conf, pp.163-168, 1998.

G. Chiu, The odd-even turn model for adaptive routing, IEEE Transactions on parallel and distributed systems, vol.11, issue.7, pp.729-738, 2000.

A. Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, F. Plateau et al., Nsynchronous Kahn networks: a relaxed model of synchrony for real-time systems, ACM SIGPLAN Notices, vol.41, issue.1, pp.180-193, 2006.

A. Cohen, L. Gérard, and M. Pouzet, Un restriction est mise: les future doivent rester local au noeud et ne peuvent pas être passés en paramètre, Proceedings of the Tenth ACM International Conference on Embedded Software, EMSOFT, pp.197-206, 2012.

F. Conti, D. Rossi, A. Pullini, I. Loi, and L. Benini, Energy-efficient vision on the PULP platform for ultra-low power parallel computing, Signal Processing Systems (SiPS), pp.1-6, 2014.

M. Cordovilla, F. Boniol, J. Forget, E. Noulard, and C. Pagetti, Developing critical embedded systems on multicore architectures: the Prelude-SchedMCore toolset, RTNS'11, 2011.
URL : https://hal.archives-ouvertes.fr/inria-00618587

R. L. Cruz, A calculus for network delay. I. Network elements in isolation, IEEE Transactions on information theory, vol.37, issue.1, pp.114-131, 1991.

W. J. Dally and C. L. Seitz, Deadlock-Free Message Routing in Multiprocessor Interconnection Networks, IEEE Trans. Comput, vol.36, issue.5, pp.547-553, 1987.
DOI : 10.1109/tc.1987.1676939

URL : https://authors.library.caltech.edu/26907/1/5206-TR-86.pdf

W. J. Dally and B. P. Towles, Principles and practices of interconnection networks (the morgan kaufmann series in computer architecture and design), 2004.

M. Daneshtalab, M. Ebrahimi, T. C. Xu, P. Liljeberg, and H. Tenhunen, A generic adaptive path-based routing method for MPSoCs, Journal of Systems Architecture, vol.57, issue.1, pp.109-120, 2011.
DOI : 10.1016/j.sysarc.2010.08.002

R. I. Davis, S. Altmeyer, L. S. Indrusiak, C. Maiza, V. Nelis et al., An extensible framework for multicore response time analysis, 2017.
DOI : 10.1007/s11241-017-9285-4

URL : https://link.springer.com/content/pdf/10.1007%2Fs11241-017-9285-4.pdf

B. Dupont-de-dinechin, Y. Durand, D. Van-amstel, and A. Ghiti, Guaranteed services of the noc of a manycore processor, Proceedings of the 2014 International Workshop on Network on Chip Architectures, pp.11-16, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01102657

B. Dupont-de-dinechin and A. Graillat, Feed-forward routing for the wormhole switching network-on-chip of the kalray mppa2 processor, Proceedings of the 10th International Workshop on Network on Chip Architectures, NoCArc'17, vol.10, pp.1-10, 2017.

B. Dupont-de-dinechin and A. Graillat, Network-on-chip service guarantees on the kalray mppa-256 bostan processor, Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, pp.35-40, 2017.

G. Durrieu, M. Faugere, S. Girbal, D. G. Pérez, C. Pagetti et al., Predictable flight management system implementation on a multicore processor, Embedded Real Time Software (ERTS'14), 2014.
URL : https://hal.archives-ouvertes.fr/hal-01121700

, Multi-core Processors, CAST-32A, FAA, Certification Authorities Software Team, 2016.

P. H. Feiler, D. P. Gluch, and J. J. Hudak, The architecture analysis & design language (AADL): An introduction, 2006.
DOI : 10.21236/ada455842

C. Ferdinand, Worst case execution time prediction by static program analysis, Parallel and Distributed Processing Symposium, p.125, 2004.
DOI : 10.1109/ipdps.2004.1303088

URL : http://www.absint.com/aiT_WCET.pdf

M. Fidler and G. Einhoff, Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communication, Third Int. IFIP-TC6 Networking Conference, 2004.

V. Firoiu, J. Y. Boudec, D. Towsley, and Z. Zhang, Theories and models for internet quality of service, Proc.of the IEEE, vol.90, issue.9, pp.1565-1591, 2002.

J. A. Fisher, Very long instruction word architectures and the ELI-512, 1983.
DOI : 10.1145/1067651.801649

C. Flanagan and M. Felleisen, The semantics of future and its use in program optimization, Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages, pp.209-220, 1995.

F. Frances, C. Fraboul, and J. Grieu, Using network calculus to optimize the afdx network, 2006.

F. Geyer and G. Carle, Network engineering for real-time networks: comparison of automotive and aeronautic industries approaches, IEEE Communications Magazine, vol.54, issue.2, pp.106-112, 2016.

A. Girault, A survey of automatic distribution method for synchronous programs, International workshop on synchronous languages, applications and programs, vol.5, 2005.

A. Girault, X. Nicollin, and M. Pouzet, Automatic Rate Desynchronization of Embedded Reactive Programs, TECS, vol.5, issue.3, pp.687-717, 2006.

C. J. Glass and L. M. Ni, The turn model for adaptive routing, ACM SIGARCH Computer Architecture News, vol.20, issue.2, pp.278-287, 1992.

C. J. Glass and L. M. Ni, The turn model for adaptive routing, Journal of the ACM (JACM), vol.41, issue.5, pp.874-902, 1994.

K. Goossens, M. Koedam, A. Nelson, S. Sinha, S. Goossens et al., Noc-based multiprocessor architecture for mixed-time-criticality applications, Handbook of Hardware/Software Codesign, pp.491-530, 2017.

R. Gorcitz, E. Kofman, T. Carle, D. Potop-butucaru, D. Simone et al., On the scalability of constraint solving for static/off-line real-time scheduling, International Conference on Formal Modeling and Analysis of Timed Systems, pp.108-123, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01250010

A. Graillat, M. Moy, P. Raymond, and B. Dupont-de-dinechin, Parallel Code Generation of Synchronous Programs for a Many-core Architecture, DATE 2018 -Design, Automation and Test in Europe, 2018.
URL : https://hal.archives-ouvertes.fr/hal-01667594

A. Graillat, H. Rihani, C. Maiza, M. Moy, P. Raymond et al., Implementation Framework for Real-Time Data-Flow Synchronous Programs on Many-Cores. Real-Time Systems

J. Grieu, Analyse et évaluation de techniques de commutation Ethernet pour l'interconnexion des systèmes avioniques, 2004.

S. Ha and E. A. Lee, Quasi-static scheduling for multiprocessor dsp, IEEE International Sympoisum on Circuits and Systems, vol.1, pp.352-355, 1991.

N. Halbwachs, Synchronous programming of reactive systems, 1993.

N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud, The synchronous data flow programming language lustre, Proceedings of the IEEE, vol.79, issue.9, pp.1305-1320, 1991.

A. Hamann, D. Dasari, S. Kramer, M. Pressler, and F. Wurst, Communication Centric Design in Complex Automotive Embedded Systems, LIPIcs, vol.76, 2017.

D. Harel and A. Pnueli, On the development of reactive systems, Logics and models of concurrent systems, pp.477-498, 1985.

B. R. Haverkort, Performance of computer communication systems: a model-based approach, 1998.

T. Henzinger, B. Horowitz, and C. Kirsch, Giotto: A time-triggered language for embedded programming, Embedded software, pp.166-184, 2001.

T. A. Henzinger, C. M. Kirsch, and S. Matic, Schedule-carrying code, International Workshop on Embedded Software, pp.241-256, 2003.

T. A. Henzinger, C. M. Kirsch, and S. Matic, Composable code generation for distributed Giotto, ACM SIGPLAN Notices, pp.21-30, 2005.

R. Holsmark, M. Palesi, and S. Kumar, Deadlock free routing algorithms for mesh topology NoC systems with regions, Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on, pp.696-703, 2006.
DOI : 10.1109/dsd.2006.36

J. Hugues and J. Delange, Model-based design and automated validation of ARINC653 architectures, 2015 International Symposium on Rapid System Prototyping (RSP), pp.3-9, 2015.

M. Ishii, J. Detrey, P. Gaudry, A. Inomata, and K. Fujikawa, Fast modular arithmetic on the kalray mppa-256 processor for an energy-efficient implementation of ecm, IEEE Transactions on Computers, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01299697

F. Jafari, M. H. Yaghmaee, M. S. Talebi, and A. Khonsari, Max-min-fair best effort flow control in network-on-chip architectures, International Conference on Computational Science, pp.436-445, 2008.

E. Kasapaki, M. Schoeberl, R. B. Sørensen, C. Müller, K. Goossens et al., Argo: A real-time network-on-chip architecture with an efficient gals implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, issue.2, pp.479-492, 2016.

S. Kehr, E. Quiñones, B. Böddeker, and G. Schäfer, Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication, DAC'15, p.42, 2015.

H. Kim, D. De-niz, B. Andersson, M. Klein, O. Mutlu et al., Bounding memory interference delay in COTS-based multi-core systems, Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.145-154, 2014.

F. Kluge, M. Schoeberl, and T. Ungerer, Support for the logical execution time model on a time-predictable multicore processor, ACM SIGBED Review, vol.13, issue.4, pp.61-66, 2016.

H. Kopetz and G. Bauer, The time-triggered architecture, Proceedings of the IEEE, vol.91, issue.1, pp.112-126, 2003.

S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg et al., A network on chip architecture and design methodology, VLSI, pp.117-124, 2002.
DOI : 10.1109/isvlsi.2002.1016885

I. Land and J. Elliott, Architecting arinc 664, part 7 (afdx) solutions. Xilinx, 2009.

L. Boudec, ,. Thiran, and P. , Network calculus: a theory of deterministic queuing systems for the internet, vol.2050, 2001.

C. Lee, H. Hahn, Y. Seo, S. L. Min, R. Ha et al., Analysis of cache-related preemption delay in fixed-priority preemptive scheduling, IEEE transactions on computers, vol.47, issue.6, pp.700-713, 1998.

E. A. Lee and S. A. Seshia, Introduction to Embedded Systems -A Cyber-Physical Systems Approach, 2017.

L. Lenzini, L. Martorini, E. Mingozzi, and G. Stea, Tight end-to-end per-flow delay bounds in fifo multiplexing sink-tree networks, Performance Evaluation, vol.63, issue.9, pp.956-987, 2006.
DOI : 10.1016/j.peva.2005.10.003

L. Levitin, M. Karpovsky, and M. Mustafa, Deadlock prevention by turn prohibition in interconnection networks, Parallel & Distributed Processing, pp.1-7, 2009.
DOI : 10.1109/ipdps.2009.5160898

X. Lin, P. K. Mckinley, and L. M. Ni, Deadlock-free multicast wormhole routing in 2-D mesh multicomputers, IEEE Transactions on Parallel and Distributed Systems, vol.5, issue.8, pp.793-804, 1994.

M. Ljung, Formal modelling and automatic verification of Lustre programs using np-tools, 1999.

M. Lo, N. Valot, F. Maraninchi, R. , and P. , Implementing a real-time avionic application on a many-core processor, 42nd European Rotorcraft Forum (ERF), 2016.
URL : https://hal.archives-ouvertes.fr/hal-01718139

M. Lv, W. Yi, N. Guan, Y. , and G. , Combining abstract interpretation with model checking for timing analysis of multicore software, Proceedings of the 2010 31st IEEE Real-Time Systems Symposium, RTSS '10, pp.339-349, 2010.

F. Maraninchi, The Argos language: Graphical representation of automata and description of reactive systems, IEEE Workshop on Visual Languages, vol.3, 1991.

A. Melani, M. Bertogna, V. Bonifaci, A. Marchetti-spaccamela, and G. Buttazzo, , 2015.

, Memory-processor co-scheduling in fixed priority systems, Proceedings of the 23rd International Conference on Real Time and Networks Systems (RTNS), pp.87-96

E. Muljadi and C. P. Butterfield, Pitch-controlled variable-speed wind turbine generation, IEEE transactions on Industry Applications, vol.37, issue.1, pp.240-246, 2001.

D. Nace, A Linear Programming Based Approach for Computing Optimal Fair Splittable Routing, Proc.of ISCC'02, p.2, 2002.

N. Naumann, Autosar runtime environment and virtual function bus, p.38, 2009.

V. A. Nguyen, D. Hardy, and I. Puaut, Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors, of Leibniz International Proceedings in Informatics (LIPIcs), vol.76, p.22, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01590421

B. Pagano, C. Pasteur, G. Siegel, and R. Kní?ek, A Model Based Safety Critical Flow for the AURIX Multi-core Platform, 9th European Congress on Embedded Real Time Software and Systems, 2018.
URL : https://hal.archives-ouvertes.fr/hal-02156195

C. Pagetti, D. Saussié, R. Gratia, E. Noulard, and P. Siron, The ROSACE case study: From Simulink specification to multi/many-core execution, IEEE RTAS'14, pp.309-318, 2014.

R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell et al., A predictable execution model for cots-based embedded systems, 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp.269-279, 2011.

R. Pellizzoni, A. Schranzhofer, J. Chen, M. Caccamo, and L. Thiele, Worst case delay analysis for memory interference in multicore systems, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.741-746, 2010.

Q. Perret, P. Maurere, E. Noulard, C. Pagetti, P. Sainrat et al., Predictable composition of memory accesses on many-core processors, 8th European Congress on Embedded Real Time Software and Systems, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01256000

Q. Perret, P. Maurere, E. Noulard, C. Pagetti, P. Sainrat et al., Temporal isolation of hard real-time applications on many-core processors, Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.1-11, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01585055

F. Plateau, Modèle n-synchrone pour la programmation de réseaux de Kahn à mémoire bornée, 2010.

W. Pree, J. Templ, P. Hintenaus, A. Naderlinger, and J. Pletzer, TDL-Steps Beyond Giotto: A Case for Automated Software Construction, Int. J. Software and Informatics, vol.5, issue.1-2, pp.335-354, 2011.

A. Rahimi, I. Loi, M. R. Kakoee, and L. Benini, A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 2011.

P. Raymond, Vérification de programmes synchrones avec Lustre/Lesar, Systèmes temps réel 1 -techniques de description et de vérification, 2006.

J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, PRET DRAM controller: Bank privatization for predictability and temporal isolation, Hardware/Software Codesign and System Synthesis (CODES+ ISSS, pp.99-108, 2011.

J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian et al., A definition and classification of timing anomalies, OASIcs-OpenAccess Series in Informatics, vol.4, 2006.

H. Rihani, M. Moy, C. Maiza, R. I. Davis, A. et al., Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor, RTNS'16, pp.67-76, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01406145

S. Saidi, R. Ernst, S. Uhrig, H. Theiling, and B. Dupont-de-dinechin, The shift to multicores in real-time and safety-critical systems, Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, pp.220-229, 2015.

J. B. Schmitt and F. A. Zdarsky, The disco network calculator: a toolbox for worst case analysis, Proceedings of the 1st international conference on Performance evaluation methodolgies and tools, p.8, 2006.

M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso et al., T-CREST: Time-predictable multi-core architecture for embedded systems, Journal of Systems Architecture, vol.61, issue.9, pp.449-471, 2015.

M. D. Schroeder, A. D. Birrell, M. Burrows, H. Murray, R. M. Needham et al., Autonet: a high-speed, self-configuring local area network using point-to-point links, 1990.

M. Shreedhar and G. Varghese, Efficient fair queueing using deficit round robin, ACM SIGCOMM Computer Communication Review, vol.25, pp.231-242, 1995.

S. Skalistis, F. Angiolini, A. Simalatsar, D. Micheli, and G. , Safe and Efficient Deployment of Data-Parallelisable Applications on Many-Core Platforms: Theory and Practice, IEEE Design & Test, 2017.

S. Skalistis and A. Simalatsar, Worst-Case Execution Time Analysis for Many-Core Architectures with NoC, pp.211-227, 2016.

A. Sodani, R. Gramunt, J. Corbal, H. Kim, K. Vinod et al., Knights landing: Second-generation intel xeon phi product, Ieee micro, vol.36, issue.2, pp.34-46, 2016.

D. Starobinski, M. Karpovsky, and L. Zakrevski, Application of Network Calculus to General Topologies using Turn-Prohibition, IEEE INFOCOM, 2002.

R. A. Stefan, A. Molnos, and K. Goossens, daelite: A tdm noc supporting qos, multicast, and fast connection set-up, IEEE Transactions on Computers, vol.63, issue.3, pp.583-594, 2014.

L. Thiele, S. Chakraborty, and M. Naedele, Real-time calculus for scheduling hard real-time systems, Circuits and Systems, 2000. Proceedings. ISCAS, vol.4, pp.101-104, 2000.

S. Tripakis, D. Bui, M. Geilen, B. Rodiers, and E. A. Lee, Compositionality in synchronous data flow: Modular code generation from hierarchical sdf graphs, ACM Transactions on Embedded Computing Systems (TECS), vol.12, issue.3, p.83, 2013.

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The worst-case execution-time problem-overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems (TECS), vol.7, issue.3, p.36, 2008.

R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister et al., Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, pp.966-978, 2009.

E. Yip, A. Girault, P. Roop, and M. Biglari-abhari, The ForeC Synchronous Deterministic Parallel Programming Language for Multicores, MCSoC'16, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01412102

M. Ziccardi, M. Schoeberl, and T. Vardanega, A time-composable operating system for the Patmos processor, Proceedings of the 30th Annual ACM Symposium on Applied Computing, pp.1892-1897, 2015.