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Si-based epitaxy processes for 14 and 10 nm CMOS technologies : Morphology and structure

Abstract : In advanced technologies, the Si-based materials epitaxy becomes more and more challenging and the morphological effects very important. The thermal treatments as well as the doping may degrade the epitaxies’ morphology resulting in considerably damaging the devices’ performances. The works presented in this thesis, aim at understanding and solving these problematics. Thus, they are focused on the study of the epitaxies’ morphology and high doping in the small patterns of the 10 and 14 nm CMOS technologies. The influence of the H2 annealing conditions on the morphology was studied. This led to determine the thermal rounding kinetics in small patterns. According to a kinetics analysis, two energies were identified: 2.9 eV and 7.7 eV. The 2.9 eV energy shows that at high temperatures, the surface diffusion is the thermal rounding main mechanism. At low temperatures, the hydrogen coverage’s increase limits even more this diffusion, greatly increasing the energy obtained. It was observed that the carrier gas pressure and its nature have a strong impact on the surface diffusion and thus modify the thermal rounding kinetics. The characterization by atomic force microscopy, of boron doped layer selectively grown, shows that the boron greatly modifies the growth’s morphology, as well as the thermal rounding. Considering a same annealing, the rounding phenomenon occurs faster in a doped pattern than in an un-doped pattern. The epitaxies developed during this work were successfully integrated to the 14 nm node sources and drains. Depending on the needs, the epitaxies can either present large and well defined facets or no facets, all of this thanks to an adequate process which was proposed and developed through this work.
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Submitted on : Thursday, March 14, 2019 - 2:48:08 PM
Last modification on : Wednesday, October 14, 2020 - 3:57:42 AM
Long-term archiving on: : Saturday, June 15, 2019 - 7:54:04 PM


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  • HAL Id : tel-02067944, version 1


Victorien Paredes-Saez. Si-based epitaxy processes for 14 and 10 nm CMOS technologies : Morphology and structure. Materials. Université de Lyon, 2017. English. ⟨NNT : 2017LYSEI032⟩. ⟨tel-02067944⟩



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