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Hardware Acceleration for Homomorphic Encryption

Abstract : In this thesis, we propose to contribute to the definition of encrypted-computing systems for the secure handling of private data. The particular objective of this work is to improve the performance of homomorphic encryption. The main problem lies in the definition of an acceleration approach that remains adaptable to the different application cases of these encryptions, and which is therefore consistent with the wide variety of parameters. It is for that objective that this thesis presents the exploration of a hybrid computing architecture for accelerating Fan and Vercauteren’s encryption scheme (FV).This proposal is the result of an analysis of the memory and computational complexity of crypto-calculation with FV. Some of the contributions make the adequacy of a non-positional number representation system (RNS) with polynomial multiplication Fourier transform over finite-fields (NTT) more effective. RNS-specific operations, inherently embedding parallelism, are accelerated on a SIMD computing unit such as GPU. NTT-based polynomial multiplications are implemented on dedicated hardware such as FPGA. Specific contributions support this proposal by reducing the storage and the communication costs for handling the NTTs’ twiddle factors.This thesis opens up perspectives for the definition of micro-servers for the manipulation of private data based on homomorphic encryption.
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Submitted on : Thursday, January 31, 2019 - 2:12:27 PM
Last modification on : Tuesday, October 20, 2020 - 11:06:59 AM
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  • HAL Id : tel-02001901, version 1



Joël Cathebras. Hardware Acceleration for Homomorphic Encryption. Hardware Architecture [cs.AR]. Université Paris Saclay (COmUE), 2018. English. ⟨NNT : 2018SACLS576⟩. ⟨tel-02001901⟩



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