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Towards hardware synthesis of a flexible radio from a high-level language

Abstract : Software defined radio (SDR) is a promising technology to tackle flexibility requirements of new generations of communication standards. It can be easily reprogrammed at a software level to implement different waveforms. When relying on a software-based technology such as microprocessors, this approach is clearly flexible and quite easy to design. However, it usually provides low computing capability and therefore low throughput performance. To tackle this issue, FPGA technology turns out to be a good alternative for implementing SDRs. Indeed, FPGAs have both high computing power and reconfiguration capacity. Thus, including FPGAs into the SDR concept may allow to support more waveforms with more strict requirements than a processor-based approach. However, main drawbacks of FPGA design are the level of the input description language that basically needs to be the hardware level, and, the reconfiguration time that may exceed run-time requirements if the complete FPGA is reconfigured. To overcome these issues, this PhD thesis proposes a design methodology that leverages both high-level synthesis tools and dynamic reconfiguration. The proposed methodology is a guideline to completely build a flexible radio for FPGA-based SDR, which can be reconfigured at run-time.
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Submitted on : Wednesday, April 3, 2019 - 3:09:08 PM
Last modification on : Thursday, November 4, 2021 - 10:54:02 AM


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  • HAL Id : tel-02089176, version 1


Mai-Thanh Tran. Towards hardware synthesis of a flexible radio from a high-level language. Networking and Internet Architecture [cs.NI]. Université Rennes 1, 2018. English. ⟨NNT : 2018REN1S072⟩. ⟨tel-02089176⟩



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