, The time allowed by the system to one channel is called "Time slot". A time-slot length is 20 micro-seconds, and is presented in figure 3.12. As the minimum time-step is a Time-Slot (TS), stimulation parameters will be expressed as a finite amount of time-slots. Within all the stimulation parameters, only Tdelay and Tinterpulse can be zeroed. The minimum timing for the others parameters equals to 1 TS, i.e. 20 µs. In order to have a 20 µs timing (minimum) for any of the temporal parameters described (fig. 1), one can set the given parameter to the hexadecimal value X"00000000". In order to get a 40 µs timing, the user got to enter the value X"00000001", and so on. In order to bypass the Delay phase or the Interphase, one should use the value X"FFFFFFFF" for those parameters. configures the Kali board peripherals in order to prepare it for stimulation. It is composed of a finite state machine, a RAM, and a SPI driver, I/O of config_kali: ? clk : (in, 1 bit, in) system clock ? reset : (in, 1 bit) system reset ? start_config : (in, 1 bit) signal from the CPU, triggers the beginning of Kali configuration ? enable_1 : (in, 1 bit) write enable signal of the RAM ? data_in_1 : (in, 1 byte)

, First line of the RAM corresponds to data for the first switch; second line is for the second switch, and so on. ? rst : (in, 1 bit) system reset ? clk : (in, 1 bit) system clock ? channel_number : (in, 4 bits) channel number being processed, from sequencer ? new_channel : (in, 1 bit) flag to announce that a new channel can be processed, from sequencer ? ram_enable : (in, 1 bit) input port of the ram. Enable ? ram_data_in : (in, 1 byte) data input of the RAM ? ram_data_out : (out, 1 byte) data output of the RAM ? ram_addr : (in, 10 bits) address input of the RAM. The 2 LSB determine which RAM is addressed, The FSM reads the RAM data, and transfers it to the SPI driver (SPI_master_switch) which sends the data through the SPI bus to the switches, at a rate of 1MHz (slck frequency)

A. Figure, 1: Stimulation parameters addresses

, Therefor it provides the direct control signals for SHIVAs circuits, specific signals for the DAC. I/O of stim_signal_mgmt: ? rst : (in, 1 bit) system reset ? clk : (in, 1 bit) system clock ? trigger : (in, 1 bit) trigger for the module to start operate the stimulation parameters ? stim_order : (in, stimulation_order) stimulation_order, from state_mgmt ? spi_busy : (in, 1 bit) flag from spi_interface, SPI still active when high ? stim_polarity : (in, 1 byte) allows polarity inversion on a given channel, MSB-> Channel, vol.7

, 1 bit) triggers the spi_interface module ? busy : (out, 1 bit) flag, on high-level as long as the module and dependences are in operation ? anodic_DC : (out, 1 byte) Anodic direct control orders for SHIVA ? cathodic_DC : (out, 1 byte) Cathodic direct control orders for SHIVA ? cs_dac : (out, 1 bit) Chip-select for the DAC ? n_rst_shiva : (out, 1 bit) SHIVA's reset signal, ? data_tx_spi : (out, 12 bits) data to be sent to the DAC through spi_interface ? trigger_spi : (out

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