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Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire

Abstract : Increasing the performance of transistors for the next decade still relies on transistor downscaling which is inevitably accompanied by an increasing complexity of the architectures and materials involved. At the beginning of this thesis, one strategy to pursue the downscaling was to replace, in a finFET architecture, the silicon channel with high-mobility semiconductor, such as In0,53Ga0,47As for the nMOS transistors. The patterning of the channel architecture by plasma etching is an essential step to overcome in the fabrication of InGaAs-based finFET transistors. Indeed, to ensure optimal performances of the device, it is crucial that the plasma etching process do not generate defects on the channel sidewalls such as a loss of stoichiometry and roughness formation. Thus, the major aim of this thesis is to pattern the 3D InGaAs channel by plasma etching with minimal sidewalls damage. For this, we investigated three plasma etching strategies. First, this work focused on the development of plasma etches process with halogen chemistries at ambient temperature (60°C). Such process leads to sloped and rough patterns due to the redeposit of low volatile InClx etch by products. Secondly, Cl2/CH4 plasma etching processes at high temperature (200°C) have been studied and developed. Anisotropic and relatively smooth patterns can be obtained using such plasma process thanks to enhanced volatility of InClx products and a SiOx sidewall passivation formation. Finally, an atomic layer etching concept has been investigated to pattern InGaAs with minimal damage. This concept consists in alternating two self-limited steps: first, an implantation step using He/O2 plasma modifies the InGaAs surface to a limited thickness. Then, the modified layer is removed by HF wet. For all these etching strategies, a methodology was implemented to perform a systematic characterization of the damage generated on the sidewalls. The Auger spectroscopy was used to determine the sidewall stoichiometry while the sidewall roughness is measured by AFM. The results from the sidewall characterizations revealed the necessity to implement a surface restoration process. It consists in oxidizing the InGaAs sidewalls with O2 plasma and to removed the oxidized layer with a HF step. This process was efficient to smooth the InGaAs pattern sidewalls but enhances an arsenic enrichment which was already present after the etching processes.
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Submitted on : Thursday, September 27, 2018 - 12:07:32 PM
Last modification on : Tuesday, October 20, 2020 - 11:34:21 AM
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  • HAL Id : tel-01882694, version 1



Maxime Bizouerne. Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes, 2018. Français. ⟨NNT : 2018GREAT030⟩. ⟨tel-01882694⟩



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