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Optimisation de la consommation d’énergie et de la latence dans les réseaux sur puces

Abstract : Thanks to the technology’s shrinking, a considerable amount of memory and computing capacity can be embedded into a single chip. This improvement leads to an important increase of the bandwidth requirements, that becomes the bottleneck of chip performances in terms of computational power. Thus, designers proposed the Network-on-Chip (NoC) as an answer to this bandwidth challenge. However, the on-chip traffic growth allowed by the NoC causes a significant rise of the chip energy consumption, which leads to a temperature increase and a reliability reduction of the chip. The development of energy optimization techniques for NoC becomes necessary.The first part of this thesis is devoted to the study of NoCs power models in order to estimate accurately the consumption of each component. Then, we can identify which ones are the most power consuming. Hence, the first contribution of this thesis has been to improve the NoC power model by replacing the lilnk power model in a NoC simulator (Noxim) by a bit-accurate one (Noxim-XT). In this way, the simulator is able to consider Crosstalk effects, a physical phenomenon that increases links energy consumption. The second part of the thesis deals with NoC energy optimization techniques. Thus, our research of optimization techniques is focused on inter-router links since their energy contribution regarding the NoC dynamic energy is significant and the dynamic energy tends to stay prominent with the shrinking technology. We proposed two optimization techniques from the study of NoC links optimizations. These two techniques present different energy / latency compromises and a possible extension of this work could be the development of a transmission strategy in order to select the right technique according to the application requirements.
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Submitted on : Tuesday, September 18, 2018 - 11:49:06 AM
Last modification on : Friday, September 25, 2020 - 3:35:57 AM
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  • HAL Id : tel-01876214, version 1


Erwan Moréac. Optimisation de la consommation d’énergie et de la latence dans les réseaux sur puces. Micro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2017. Français. ⟨NNT : 2017LORIS467⟩. ⟨tel-01876214⟩



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