We focus on one of the bus channels, the "read data" channel. This channel uses a variation of the handshake protocol, defined as follows: 1. assume always (ready && ! valid) ? next ready 2. assert always (! ready && valid) ? next valid 3. assume always (ready && valid) ? next ! ,
, ? BUS1: the system control interface, by which the system reads data from the environment
, Due to the size of the design, we need some abstraction to prune the state-space, for the model checker to give a conclusive result. We use our UCEGAR algorithm, ? BUS2: the system interface by which the interruptions are transmitted to the CPU
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