Skip to Main content Skip to Navigation

Conclusive formal verification of clock domain crossing properties

Abstract : Modern hardware designs typically comprise tens of clocks to optimize consumption and performance to the ongoing tasks. With the increasing number of clock-domain crossings as well as the huge complexity of modern SoCs, formally proving the functional integrity of data propagation became a major challenge. Several issues arise: setting up the design in a realistic mode, writing protocol assumptions modeling the environment, facing state-space explosion, analyzing counter-examples, ...The first contribution of this thesis aims at reaching a complete and realistic design setup. We use parametric liveness verification and a structural analysis of the design in order to identify behaviors of the clock and reset trees. The second contribution aims at avoiding state-space explosion, by combining localization abstractions of the design, and counter-example analysis. The key idea is to use counterexample-guided abstraction refinement as the algorithmic back-end, where the user influence the course of the algorithm based on relevant information extracted from intermediate abstract counterexamples. The third contribution aims at creating protocol assumptions for under-specified environments. First, multiple counter-examples are generated for an assertion, with different causes of failure. Then, information is mined from them and transformed into realistic protocol assumptions.Overall, this thesis shows that a conclusive formal verification can be obtained by combining inexpensive structural analysis along with exhaustive model checking.
Document type :
Complete list of metadatas

Cited literature [86 references]  Display  Hide  Download
Contributor : Abes Star :  Contact
Submitted on : Friday, September 7, 2018 - 11:39:07 AM
Last modification on : Wednesday, October 7, 2020 - 1:20:38 PM
Long-term archiving on: : Saturday, December 8, 2018 - 2:33:30 PM


Version validated by the jury (STAR)


  • HAL Id : tel-01870205, version 1




Guillaume Plassan. Conclusive formal verification of clock domain crossing properties. Symbolic Computation [cs.SC]. Université Grenoble Alpes, 2018. English. ⟨NNT : 2018GREAT021⟩. ⟨tel-01870205⟩



Record views


Files downloads