I. For and .. , , p.70

I. For and .. , , p.70

.. , AIX4-stream -IPs using the blocking mode, p.71

.. , AIX4-stream -IPs using the non-blocking mode, p.72

A. Graph and .. , , p.76

.. An-example-of-channels-aggregation, , p.76

, Consumption rates: the most favorable case and the unfavorable case, p.77

.. , Consumption rates of an actor in different cases, p.78

.. , The flow chart of conformance checking and modification, p.79

.. , A graph (consistent) presented in SDF model, p.81

A. and G. , , p.81

.. , A graph (inconsistent) presented in SDF model, p.82

.. Building-admittance-pattern-for-example-9,

, Infinite number of choices when building an admittance pattern, p.88

.. Building-admittance-pattern-for-example-11, , p.91

.. , An ASAP design: filtering a stereo signal, p.93

F. , Demonstration case: a graph of blocks for real-time image processing on an, p.97

.. , The flow chart of working process in BlAsT, p.104

A. Demo-design-in-blast and .. , , p.106

.. An-example-of-reference-file, , p.107

.. Parameter-setting-in-blast,

.. An-example-of-implementation-file, , p.109

.. , An example of @for instruction in an implementation file, p.110

F. , The patterns definition for a blur, p.110

.. , An example of generated VHDL code for a top group, p.112

.. , An example of wheels detector design in BlAsT, p.113

C. Detection-of-an-incompatible, , p.114

C. Investigating-an-incompatible, , p.114

C. Solving-an-incompatible,

A. Truth-table-for-boolean, , p.31

.. , Characteristics of 5 ? 7 and 5 ? 8 interpolators, p.68

O. Production-counters, , p.98

.. Production-patterns-for-different-camera-clocks, , p.99

.. Resources-consumption, , p.99

M. and M. , combination of test parameters with SDF-AP model, p.100

.. , Test results of two examples of timings, p.100

K. Du, S. Domas, and M. Lenczner, Actors with Stretchable Access Patterns, Integration, the VLSI Journal, 2018.

, Techniques for System Analysis Based on ASAP Model, ACM SIGMETRICS 2018, the International Conference on Measurement and Modeling of Computer Systems, 2018.

K. Du, J. Liu, X. Zhang, J. Feng, Y. Guan et al., A Graph-based Algorithm on Semi-supervised Image Classification, ICCS 2018, the 18th International Conference on Computational Science, 2018.

K. Du, S. Domas, and M. Lenczner, A solution to overcome some limitations of SDF based models, 2018 IEEE International Conference on Industrial Technology (ICIT), 2018.
DOI : 10.1109/ICIT.2018.8352384

K. Du, S. Domas, M. Wu, and M. Lenczner, A Hole-Filling Framework Based on DIBR and Improved Criminisi's Inpainting Algorithm for 3D Videos, Proceedings of the 2017 International Conference on Cloud and Big Data Computing , ICCBDC 2017, pp.119-124, 2017.
DOI : 10.1109/MMSP.2010.5662013

K. Du, S. Domas, M. Lenczner, and G. Zhang, An Improved Algorithm Based on SURF for MR Infant Brain Image Registration, ICIC 2016, the 12th International Conference on Intelligent Computation, Intelligent Computing Theories and Application, pp.458-470, 2016.
DOI : 10.1016/j.jvcir.2013.02.005

Y. D. Guan, R. F. Zhu, J. Y. Feng, K. Du, and X. R. Zhang, Research on Algorithm of Human Gait Recognition Based on Sparse Representation, 2016 Sixth International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC), pp.405-410, 2016.
DOI : 10.1109/IMCCC.2016.71

M. Lenczner, B. Yang, S. Cogan, S. Domas, D. Ke et al., Temperature control of an SThM micro-probe with an heat source estimator and a lock-in measurement, 2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp.1-8, 2016.
DOI : 10.1109/EuroSimE.2016.7463351

M. Lenczner, B. Yang, R. Couturier, S. Domas, K. Du et al., Two-scale modeling and model-based control law of temperature in an SThM probe, Eurotherm Seminar No 109, 2015.


O. Cores, A. Fpga, and . Development,

M. Benazouz, O. Marchetti, A. Munier-kordon, and T. Michel, A new method for minimizing buffer sizes for Cyclo-Static Dataflow graphs, 2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, pp.11-20, 2010.
DOI : 10.1109/ESTMED.2010.5666980

URL : https://hal.archives-ouvertes.fr/hal-00461647

M. Benazouz, O. Marchetti, A. Munier-kordon, and P. Urard, A new approach for minimizing buffer capacities with throughput constraint for embedded system design, ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2010, pp.1-8, 2010.
DOI : 10.1109/AICCSA.2010.5586972

URL : https://hal.archives-ouvertes.fr/hal-00368648

A. Benveniste and P. L. Guernic, Hybrid dynamical systems theory and the Signal language, IEEE Transactions on Automatic Control, vol.35, issue.5, pp.535-546, 1990.
DOI : 10.1109/9.53519

URL : https://hal.archives-ouvertes.fr/inria-00075715

A. Benveniste, P. L. Guernic, Y. Sorel, and M. Sorine, A denotational theory of synchronous reactive systems, Information and Computation, vol.99, issue.2, pp.192-230, 1992.
DOI : 10.1016/0890-5401(92)90030-J

URL : https://hal.archives-ouvertes.fr/hal-00549783

B. Bhattacharya, S. Shuvra, and . Bhattacharyya, Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001.
DOI : 10.1109/78.950795

S. Bhattacharyya, E. Murthy, and . Lee, Software synthesis from dataflow graphs, volume 360 of the kluwer international series in engineering and computer science, 1996.

G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete, Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996.
DOI : 10.1109/78.485935

G. Bilsen, M. Engels, R. Lauwereins, A. Jean, and . Peperstraete, Cyclostatic data flow, Acoustics, Speech, and Signal Processing ICASSP-95., 1995 International Conference on, pp.3255-3258, 1995.

A. Bonfietti, L. Benini, M. Lombardi, and M. Milano, An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.897-902, 2010.
DOI : 10.1109/DATE.2010.5456924

T. Joseph, S. Buck, . Ha, A. Edward, . Lee et al., Ptolemy: A framework for simulating and prototyping heterogeneous systems, 1994.

J. Tobin, B. Edward, and A. Lee, Scheduling dynamic dataflow graphs with bounded memory using the token flow model, Acoustics, Speech, and Signal Processing IEEE International Conference on, pp.429-432, 1993.

B. Cook, Legacy of the transputer, Architectures, Languages and Techniques, IOS. Citeseer, 1999.

M. Edwards and P. Green, The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware, International Workshop on Field Programmable Logic and Applications, pp.739-748, 2000.
DOI : 10.1007/3-540-44614-1_78

J. Eker, J. ¨. Janneck, A. Edward, J. Lee, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, pp.127-144, 2003.
DOI : 10.1109/JPROC.2002.805829

M. Engels, G. Bilson, R. Lauwereins, and J. Peperstraete, Cycle-static dataflow: model and implementation, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers, pp.503-507, 1994.
DOI : 10.1109/ACSSC.1994.471504

P. Feautrier, Fine-grain scheduling under resource constraints, International Workshop on Languages and Compilers for Parallel Computing, pp.1-15
DOI : 10.1007/BFb0025867

D. Fimmel and J. M. Uller, OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS, International Journal of Foundations of Computer Science, vol.24, issue.2, pp.697-718, 2001.
DOI : 10.1007/BF02106824

A. R. Om-prakash-gangwal, K. Goossens, S. G. Pestana, and E. Rijpkema, Building predictable systems on chip: An analysis of guaranteed communication in the aethereal network on chip, Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices, pp.1-36, 2005.

S. Kang and . Gatlin, Trials and tribulations of debugging concurrency, Queue, vol.2, issue.7, pp.66-73, 2004.

M. Geilen and T. Basten, Requirements on the Execution of Kahn Process Networks, European Symposium on Programming, pp.319-334, 2003.
DOI : 10.1007/3-540-36575-3_22

M. Geilen and T. Basten, Reactive process networks, Proceedings of the fourth ACM international conference on Embedded software , EMSOFT '04, pp.137-146, 2004.
DOI : 10.1145/1017753.1017778

M. Geilen, S. Tripakis, and M. Wiggers, The earlier the better, Proceedings of the 14th international conference on Hybrid systems: computation and control, HSCC '11, pp.23-32, 2011.
DOI : 10.1145/1967701.1967707

. Amir-hossein-ghamarian, T. Mcw-geilen, S. Basten, and . Stuijk, Parametric throughput analysis of synchronous data flow graphs, Design, Automation and Test in Europe DATE'08, pp.116-121, 2008.

. Amir-hossein-ghamarian, T. Mcw-geilen, . Basten, D. Bart, M. R. Theelen et al., Liveness and boundedness of synchronous data flow graphs, Formal Methods in Computer Aided Design FMCAD'06, pp.68-75, 2006.

. Amir-hossein-ghamarian, S. Mcw-geilen, T. Stuijk, . Basten, D. Bart et al., Throughput analysis of synchronous data flow graphs, Application of Concurrency to System Design Sixth International Conference on, pp.25-36, 2006.

S. Amir-hossein-ghamarian, T. Stuijk, . Basten, . Mcw-geilen, D. Bart et al., Latency minimization for synchronous data flow graphs, Digital System Design Architectures, Methods and Tools 10th Euromicro Conference on, pp.189-196, 2007.

S. Valentin-gheorghita, M. Palkovic, J. Hamers, A. Vandecappelle, S. Mamagkakis et al., System-scenario-based design of dynamic embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.14, issue.1, p.3, 2009.

A. Ghosal, R. Limaye, K. Ravindran, S. Tripakis, A. Prasad et al., Static dataflow with access patterns, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.656-663, 2012.
DOI : 10.1145/2228360.2228479

A. Gill, Introduction to the Theory of Finite-State Machines, 1962.

A. Girault, B. Lee, A. Edward, and . Lee, Hierarchical finite state machines with multiple concurrency models IEEE Transactions on computer-aided design of integrated circuits and systems, pp.742-760, 1999.

G. Goavec-merou, G ´ enérateuren´enérateur de coprocesseur pour le traitement de donnéesdonn´données en flux (vidéovid´vidéo ou similaire) sur FPGA

S. Goddard and K. Jeffay, The synthesis of real-time systems from processing graphs, Proceedings. Fifth IEEE International Symposium on High Assurance Systems Engineering (HASE 2000), pp.177-186, 2000.
DOI : 10.1109/HASE.2000.895457

R. Goering, Multicore design strives for balance... but programming, debug tools complicate adoption, Electronics Engineering Times, 2006.

R. Govindarajan, R. Guang, P. Gao, and . Desai, Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks Journal of VLSI signal processing systems for signal, image and video technology, pp.31207-229, 2002.

W. Haid, K. Huang, I. Bacivarov, and L. Thiele, Multiprocessor SoC software design flows, IEEE Signal Processing Magazine, vol.26, issue.6, 2009.
DOI : 10.1109/MSP.2009.934111

J. Horstmannshoff and H. Meyr, Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs, Proceedings 12th International Symposium on System Synthesis, pp.38-43, 1999.
DOI : 10.1109/ISSS.1999.814258

C. Hsu, F. Keceli, M. Ko, S. Shahparnia, S. Shuvra et al., DIF: An Interchange Format for Dataflow-Based Design Tools, International Workshop on Embedded Computer Systems, pp.423-432, 2004.
DOI : 10.1007/978-3-540-27776-7_44

C. Hsu, M. Ko, S. Shuvra, and . Bhattacharyya, Software synthesis from the dataflow interchange format, Proceedings of the 2005 workshop on Software and compilers for embedded systems , SCOPES '05, pp.37-49, 2005.
DOI : 10.1145/1140389.1140394

, Xilinx Inc. Xilinx Core Generator. Xilinx Inc., ISE Design Suite, vol.12, 2010.

, Accellera Systems Initiative

C. National, F. Labview, . Janneck, D. Ian, . Miller et al., Matthieu Wipliez, and Mickä el Raulet. Synthesizing hardware from dataflow programs, Journal of Signal Processing Systems, vol.63, issue.2, pp.241-249, 2009.

A. Jerraya and W. Wolf, Multiprocessor systems-on-chips, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00012749

H. Jung, H. Yang, and S. Ha, Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis, Journal of Signal Processing Systems, vol.9, issue.2, pp.13-34, 2008.
DOI : 10.1109/2.347998

G. Kahn, The semantics of a simple language for parallel programming, " information processing'74: Proceedings of the ifip congress, pp.471-475, 1974.

L. Karam, I. Alkamal, A. Gatherer, A. Gene, . Frantz et al., Trends in multicore DSP platforms, IEEE Signal Processing Magazine, vol.26, issue.6, 2009.
DOI : 10.1109/MSP.2009.934113

H. Kee, S. Shuvra, J. Bhattacharyya, and . Kornerup, Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp.136-143, 2010.
DOI : 10.1109/ICSAMOS.2010.5642074

R. Lauwereins, M. Engels, M. Adéad´adé, and J. Peperstraete, Grape-II: a system-level prototyping environment for DSP applications, Computer, vol.28, issue.2, pp.35-43, 1995.
DOI : 10.1109/2.347998

P. Le, G. , and T. Gautier, Data-flow to von Neumann: the SIGNAL approach, 1990.
URL : https://hal.archives-ouvertes.fr/inria-00075329

A. Edward and . Lee, Consistency in dataflow graphs, IEEE Transactions on Parallel and Distributed systems, vol.2, issue.2, pp.223-235, 1991.

A. Edward and . Lee, Finite state machines and modal models in ptolemy ii, 2009.

A. Edward, S. Lee, G. David, and . Messerschmitt, Scheduling strategies for multiprocessor real-time dsp, Global Telecommunications Conference and Exhibition'Communications Technology for the 1990s and Beyond'(GLOBECOM) Synchronous data flow. Proceedings of the IEEE, pp.1279-12831235, 1987.

A. Edward, S. Lee, and . Neuendorffer, Concurrent models of computation for embedded software, IEE Proceedings-Computers and Digital Techniques, pp.239-250, 2005.

A. Edward, . Lee, M. Thomas, and . Parks, Dataflow process networks. Proceedings of the IEEE, pp.773-801, 1995.

A. Edward, H. Lee, and . Zheng, Leveraging synchronous language principles for heterogeneous modeling and design of embedded systems, Proceedings of the 7th ACM & IEEE international conference on Embedded software, pp.114-123, 2007.

E. Ashford, L. David, and G. Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on computers, vol.100, issue.1, pp.24-35, 1987.

M. Leung, T. Mandl, A. Edward, E. Lee, C. Latronico et al., Scalable semantic annotation using latticebased ontologies, International Conference on Model Driven Engineering Languages and Systems, pp.393-407, 2009.
DOI : 10.1007/978-3-642-04425-0_31

URL : http://chess.eecs.berkeley.edu/pubs/611/ModelOntology_MODELS2009_PrepubVersion.pdf

W. Liu, M. Yuan, X. He, Z. Gu, and X. Liu, Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization, 2008 Real-Time Systems Symposium, pp.492-504, 2008.
DOI : 10.1109/RTSS.2008.49

G. Martin, Esl requirements for configurable processor-based embedded system design. IP-SoC, pp.15-20, 2005.

G. Martin, Overview of the MPSoC design challenge, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.274-279, 2006.
DOI : 10.1145/1146909.1146980

. Inc, . Mathworks, and . Coder,

. Inc, . Mathworks, and . Simulink,

M. Mattavelli, S. Shuvra, J. Bhattacharyya, . Eker, G. Carl-von-platen et al., Opendf?a dataflow toolset for reconfigurable hardware and multicore systems, ACM SIGARCH Computer Architecture News, Special, vol.36, pp.29-35, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00398827

O. Moreira, J. Mol, M. Bekooij, and J. Van-meerbergen, Multiprocessor Resource Allocation for Hard-Real-Time Streaming with a Dynamic Job-Mix, 11th IEEE Real Time and Embedded Technology and Applications Symposium, pp.332-341, 2005.
DOI : 10.1109/RTAS.2005.33

M. Orlando, . Moreira, J. Marco, and . Bekooij, Self-timed scheduling analysis for realtime applications, EURASIP Journal on Advances in Signal Processing, vol.2007, issue.1, pp.1-14, 2007.

T. Murata, Petri nets: Properties, analysis and applications, Proceedings of the IEEE, pp.541-580, 1989.
DOI : 10.1109/5.24143

M. Thomas and . Parks, Bounded scheduling of process networks, 1995.

M. Thomas, J. L. Parks, . Pino, A. Edward, and . Lee, A comparison of synchronous and cycle-static dataflow, Signals, Systems and Computers Conference Record of the Twenty-Ninth Asilomar Conference on, pp.204-210, 1995.

D. Andy and . Pimentel, The artemis workbench for system-level performance evaluation of embedded systems, International Journal of Embedded Systems, vol.3, issue.3, pp.181-196, 2008.

J. Luis-pino, S. Shuvra, . Bhattacharyya, A. Edward, and . Lee, A hierarchical multiprocessor scheduling framework for synchronous dataflow graphs, 1995.

J. Luis-pino, S. Ha, A. Edward, . Lee, T. Joseph et al., Software synthesis for dsp using ptolemy Journal of VLSI signal processing systems for signal, image and video technology, pp.7-21, 1995.

P. Poplavko, T. Basten, M. Bekooij, J. Van-meerbergen, and B. Mesman, Task-level timing models for guaranteed performance in multiprocessor networks-on-chip, Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems , CASES '03, pp.63-72, 2003.
DOI : 10.1145/951710.951721

K. Ravindran, A. Ghosal, R. Limaye, G. Wang, G. Yang et al., Analysis techniques for static dataflow models with access patterns, Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on, pp.1-8, 2012.

G. Roquier, M. Wipliez, . Mickä-el-raulet, W. Jorn, . Janneck et al., Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study, 2008 IEEE Workshop on Signal Processing Systems, pp.281-286, 2008.
DOI : 10.1109/SIPS.2008.4671776

URL : https://hal.archives-ouvertes.fr/hal-00336516

C. Rowen, Engineering the complex SOC: fast, flexible design with configurable processors, 2008.

A. Sangiovanni, -. Vincentelli, and G. Martin, Platform-based design and software design methodology for embedded systems, IEEE Design & Test of Computers, vol.18, issue.6, pp.23-33, 2001.
DOI : 10.1109/54.970421

S. Shih, Code generation for vsp software tool in ptolemy, MS Report, Plan II, 1994.

S. Sriram, S. Shuvra, and . Bhattacharyya, Embedded multiprocessors: Scheduling and synchronization, 2009.
DOI : 10.1201/9781420048025

S. Stuijk, T. Basten, H. Mcw-geilen, and . Corporaal, Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs, Proceedings of the 44th annual Design Automation Conference Marc Geilen, and Twan Basten. Sdf3: Sdf for free. In ACSD, pp.777-782, 2006.

S. Stuijk, M. Geilen, and T. Basten, Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs, IEEE Transactions on Computers, vol.57, issue.10, pp.1331-1345, 2008.
DOI : 10.1109/TC.2008.58

S. Stuijk, M. Geilen, B. Theelen, and T. Basten, Scenario-aware dataflow: Modeling, analysis and implementation of dynamic applications, 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp.404-411, 2011.
DOI : 10.1109/SAMOS.2011.6045491

D. Bart, . Theelen, C. Marc, T. Geilen, . Basten et al., A scenario-aware data flow model for combined long-run average and worst-case performance analysis, Proceedings of the Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design MEMOCODE'06. Proceedings, pp.185-194, 2006.

D. Bart, . Theelen, S. Mcw-geilen, S. Stuijk, T. Valentin-gheorghita et al., , 2008.

S. Tripakis, H. Andrade, A. Ghosal, R. Limaye, K. Ravindran et al., Correct and non-defensive glue design using abstract models, Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, pp.59-68, 2011.
DOI : 10.1145/2039370.2039382

S. Tripakis, R. Limaye, K. Ravindran, G. Wang, H. Andrade et al., Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware, Journal of Signal Processing Systems, vol.25, issue.10, pp.1-21, 2015.
DOI : 10.1007/978-3-540-30569-9_3

P. Parishwad and . Vaidyanathan, Multirate systems and filter banks. Pearson Education India, 1993.

A. Valmari, The state explosion problem In Lectures on Petri nets I: Basic models, pp.429-528, 1998.

C. Von, P. , and J. Eker, Efficient realization of a cal video decoder on a mobile terminal (position paper), Signal Processing Systems, pp.176-181, 2008.

G. Wang, R. Allen, A. Hugo, A. Andrade, and . Sangiovanni-vincentelli, Communication storage optimization for static dataflow with access patterns under periodic scheduling and throughput constraint, Computers & Electrical Engineering, vol.40, issue.6, pp.1858-1873, 2014.
DOI : 10.1016/j.compeleceng.2014.05.002

M. Wiggers, M. Bekooij, P. Jansen, and G. Smit, Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis , CODES+ISSS '06, pp.10-15, 2006.
DOI : 10.1145/1176254.1176260

H. Maarten, . Wiggers, J. Marco, . Bekooij, G. Pierre et al., Efficient computation of buffer capacities for cyclo-static real-time systems with backpressure, 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07), pp.281-292, 2007.

H. Maarten, . Wiggers, J. Marco, . Bekooij, J. Gerard et al., Efficient computation of buffer capacities for cyclo-static dataflow graphs, 44th ACM/IEEE Design Automation Conference, pp.658-663, 2007.

H. Maarten, . Wiggers, J. Marco, . Bekooij, J. Gerard et al., Buffer capacity computation for throughput constrained streaming applications with data-dependent inter-task communication, Real-Time and Embedded Technology and Applications Symposium, pp.183-194, 2008.

H. Maarten, . Wiggers, J. Marco, . Bekooij, J. Gerard et al., Buffer capacity computation for throughput-constrained modal task graphs, ACM Transactions on Embedded Computing Systems (TECS), vol.10, issue.2, p.17, 2010.

C. Michael, . Williamson, A. Edward, and . Lee, Synthesis of parallel hardware implementations from synchronous dataflow graph specifications, Signals, Systems and Computers Conference Record of the Thirtieth Asilomar Conference on, pp.1340-1343, 1996.

H. Zheng, A. Edward, and . Lee, Operational semantics of hybrid systems Document generated with L AT E X and: the L AT E X style for PhD Thesis created by S. Galland ? http://www.multiagent.fr/ThesisStyle the tex-upmethodology package suite ? http, 2007.