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Building and analyzing processing graphs on FPGAs with strong time and hardware constraints

Abstract : With the development of electronic industry, a growing number of projects require real-time streaming applications on embedded platforms. These comprise increasingly high hardware and timing constraints, which leads to the use of FPGAs (Field Programmable Gate Arrays). Usually, the designer should have a good knowledge of programming with VHDL or Verilog HDL. Unfortunately, only specialists can do it, because this needs a lot of training and practices to master these architectures. Furthermore, even for specialists, the process of development is quite time consuming. Therefore, how to develop a tool to help non-expert users working on FPGA is a promising but challenging work.Tools like Simulink+HDL coder provide a graphical interface to create a design, by putting functional blocks on a layer and to connect them. Nevertheless, such tools are generally suffering from two flaws. One is that they do not take the physical characteristics of the target architecture of the application into account, including that of the selected FPGA. The other one is that they do not check whether a data stream is processed correctly by the design, besides creating many test-benches, which is tedious and time consuming for the developer. Therefore, they are not suitable to produce applications in real-time environment and high hardware constraints.In order to manage the ever-increasing size and complexity of designs, the abstraction is gradually more and more essential. Some models have emerged to represent a design as a graph of actors (i.e. blocks), with a static analysis of the graph execution. Nevertheless, they have an unfaithful description of the behavior real architectures like an FPGA.In this dissertation, we concentrate on the study of a novel model and software tool that can help non-expert users for automatic design of FPGA implementations correctly. The main contributions are summarized as follows:1. The limits of existing SDF models, in particular those of the SDF-AP model, are described and illustrated by the analysis of characteristic examples. The two most common problems encountered in block assembly implementations are the production of incorrect results and the infinite growth of buffer size.2. We propose a new model called Actors Stretchable Access Patterns (ASAP) that describes the hardware behaviors as efficiently and precisely as possible. This is a novel way to address the scheduling problem of actors, adapted to FPGA architectures. It opens the possibility to determine the execution correctness mathematically without launching complex simulations. It can not only model actors' behaviors properly, but also avoid the above mentioned drawbacks. Algorithms that implement these principles also provided.3. We investigate strategies and related algorithms to analyze a graph representing a designed system. Its correctness can be analyzed by a series of algorithms, such as sample rate checking and pattern compatibility checking. The decimation rate or the delay length to be applied on actor's input can be computed when a correctness failure is detected. This increases the number of possible real FPGA implementations covered by the block assembly method.4. A software tool based on the concept of functional block graph is also developed. It is called BlAsT (Block Assembly Tool) and aims to compensate the drawbacks of other tools based on the same concepts, as for example Simulink + HDL coder. In BlAsT, the proposed ASAP model and related algorithms are used to check that for a given input stream, whether the system can produce a correct result and finally generate VHDL code directly usable on a real FPGA-based board. Otherwise, the tool determines the required decimations and modifications on the graph automatically. It makes a user without any programming skills to make designs on FPGAs thanks to the friendly graphic interface.
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Submitted on : Friday, August 31, 2018 - 4:58:06 PM
Last modification on : Thursday, January 13, 2022 - 12:00:21 PM
Long-term archiving on: : Saturday, December 1, 2018 - 4:10:52 PM


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  • HAL Id : tel-01865542, version 1


Ke Du. Building and analyzing processing graphs on FPGAs with strong time and hardware constraints. Programming Languages [cs.PL]. Université Bourgogne Franche-Comté, 2018. English. ⟨NNT : 2018UBFCA005⟩. ⟨tel-01865542⟩



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