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Conception d'un ADC de résolution 8 bits basse consommation et 2 GHz de fréquence d'échantillonnage en technologie CMOS 180 nm

Abstract : After a a brief recall of the context this research work have been carried, the 1st chapter present the common analog to digital converters (ADC) characteristics with their figures of merit (FoM). A relevant state of the art on realized ADC architectures is presented. A particular emphasis has been done on 180 nm CMOS process node. This preliminary work gives a pertinent overview of the faced challenge. Multi step analog sampling architectures have been avoided from the study because of the transistors limited frequency performances. Chapter 2 presents the different implementations of the Flash digital sampling ADC family architecture. The TIQ architecture embedding in the 180 nm CMOS process are detailed in this chapter. Chapter 3 details the study and the design of an other digital sampling ADC family architecture on 180 nm CMOS process i.e. the signal folding architecture. This 1st part of the document conclude with the choice of the Flash ADC architecture. The building bloc design for this ADC are detailed in the following chapters constituting the part II. Chapter 4 is dedicated to the study and the design on 180 nm CMOS process of the latch comparator responsible of the 2 GHz sampling constraint of the overall ADC. As the retained comparator architecture input refereed non linearity defined the gain constraints of the preamplifier stage, the preamplifier is presented in the next chapter. Chapter 5 present the different characteristics and techniques of the quantifier stage. The comparator preamplifier stage with its different actives loads, its passive full differential transposition and the retained architecture are detailed. The QV technique and its embedding in the retained preamplifier architecture are presented. The thermometric 1 to binary encoder tree is presented in chapter 6. Two implementations of this encoding are studied and design on the Front-End (FE) level. The 1st one is a pipelined Wallace tree realized with a register transfer level (RTL) code on VHDL hardware description language. The synthesis flow on CMOS pull-up pull-down 2 combinatorial logic and rising edge flip flops are used for this architecture. The other architecture is designed using 1 bits multiplexers combinatorial pipelined with pass gated D latches with a full custom schematic implementation. Chapter 7 presents the limitations and the embedding of the interpolation with the retained preamplifier and comparator latch. The study of common drain source follower (CDSF) pairs insertion, mandatory for the biasing of the preamplifier input stage to reach the 8 bits resolution is studied with details. Finally, Monte Carlo sampling mismatch 3 analysis on the resistor references are studied by comparing different topologies and sizing. The overall ADC synoptic is presented with the retained cells and techniques. The bottom-up design approach, mandatory for analog and full-custom design, exposed in this 2nd part conclude on the choice to design a proof of concept ASIC (BuBlC1) including all the critical piece of circuits of the overall ADC with added value and potentially critical for signal conversion. The top-down approach for this ASIC design is detailed in the IIIrd part with the overall ASIC synoptic of the BuBlC1 ASIC sent to multi project wafer (MPW) foundry run integrating all the critical cells.The FE design of this ASIC with its clock tree and its input/output PAD are presented in chapter 8. The Back-End design with the retained cells layout in part II with the cells integration in clusters are presented in chapter 9 with the pad-ring and final integration in digital and analog macro-cells cores.
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Submitted on : Thursday, July 19, 2018 - 10:29:24 AM
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Gabriel Puech. Conception d'un ADC de résolution 8 bits basse consommation et 2 GHz de fréquence d'échantillonnage en technologie CMOS 180 nm. Electronique. Université Clermont Auvergne, 2017. Français. ⟨NNT : 2017CLFAC094⟩. ⟨tel-01844086⟩



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