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Optimisation de l'épitaxie VLS du semiconducteur 4H-SiC : Réalisation de dopages localisés dans 4H-SiC par épitaxie VLS et application aux composants de puissance SiC

Abstract : The objective of the VELSIC project has been to demonstrate the feasibility of 1 µm deep p+/n- junctions with high electrical quality in 4H-SiC semiconductor, in which the p++ zone is implemented by an original low-temperature localized epitaxy process ( 1100 - 1200 °C ), performed in the VLS (Vapor - Liquid - Solid) configuration. This innovative epitaxy doping technique uses the monocrystalline SiC substrate as a crystal growth seed. On the substrate (0001-Si) surface, buried patterns of Al - Si stack are fused to form liquid islands which are fed with carbon by C3H8 in the gas phase. This method is investigated as a possible higher performance alternative to the ion implantation process, currently used by all manufacturers of SiC devices, but which still experiences problematic limitations that are yet unresolved to date. Although the main focus of the study has been set on the optimization of localized VLS epitaxy, our works have explored and optimized all the facets of the complete process of test diodes, from the etching of patterns in the SiC substrate up to the electrical I - V characterization of true pn diodes with ohmic contacts on both sides.Our results have confirmed the need to limit the growth rate down to 1 µm/h to maintain good crystallinity of the epitaxial material. It has also highlighted the direct action of the radiofrequency electromagnetic field on the liquid phase, leading to a very strong influence of the diameter of the etched patterns on the thickness of the deposited SiC. A nearly complete filling of the 1 µm deep trenches with very high p++ doping has been demonstrated. Using optimized VLS growth parameters, p+/n- diode demonstrators have been processed and tested. On the best samples, without passivation or peripheral protection, high direct-current threshold voltages, between 2.5 and 3 V, were measured for the first time without any high-temperature annealing after epitaxy. These threshold voltage values correspond to the expected values for a true p-n junction on 4H-SiC. Current densities of several kA/cm2 have also been injected at voltages around 5 - 6 V. Under reverse bias conditions, no breakdown is observed up to 400 V and low leakage current densities at low electric field, in the range 10 - 100 nA/cm2, have been measured. All these advances align with or exceed state-of-the-art results for such simple SiC devices, obtained using any doping technique
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  • HAL Id : tel-01838259, version 1

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Selsabil Sejil. Optimisation de l'épitaxie VLS du semiconducteur 4H-SiC : Réalisation de dopages localisés dans 4H-SiC par épitaxie VLS et application aux composants de puissance SiC. Matériaux. Université de Lyon, 2017. Français. ⟨NNT : 2017LYSE1170⟩. ⟨tel-01838259⟩

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