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Fabrication de CMOS à basse température pour l'intégration 3D séquentielle

Abstract : As the scaling of transistors following Moore’s law seems to slow down due to physical, technological and economical barriers, it becomes mandatory to find alternatives to cope with the increasing demand in electronics: computing and telecommunication, smart and interconnected objects, medical and biological fields… To that end, the use of the third dimension, in opposition to the planar processing of electronical devices, appears to be a promising option. Indeed, 3D integration allows incorporating more devices per area by stacking them at a lower technological and economical cost than scaling. More specifically, 3D sequential or CoolCubeTM at CEA-Leti allows benefiting fully from the third dimension by processing successively one on top of each other each level of a die, allowing an optimal alignment of single transistors at each layer. However, several technological barriers specific to 3D Sequential Integration need then to be alleviated.In this work, we will study the reduction of thermal budget for the transistors fabrication, which is required to not damage bottom levels during the processing of top devices. First, we will define the maximal thermal budget in order not to degrade bottom layers prior to identifying the technological modules impacted during the fabrication of a transistor. We will then see in this work that not only new materials need to be studied, but also new processes and new annealing techniques. Specifically, we will first evaluate the use of low-k dielectrics as gate offset spacers, allowing the improvement of devices dynamic performance. Then we will present different strategies of surface preparation and epitaxial growth at low temperature for the formation of raised sources and drains. Finally, we will study the impact of a low thermal budget process flow along with novel microwaves and laser annealing techniques on the gate stack properties. In particular, we will see that the biggest challenge in a low thermal budget integration is to get a good reliability of transistors. This study leads to a proposed low thermal budget process flow for transistor fabrication compatible with 3D Sequential Integration.
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Submitted on : Wednesday, June 27, 2018 - 10:19:27 AM
Last modification on : Thursday, June 11, 2020 - 5:04:07 PM
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  • HAL Id : tel-01824340, version 1




Cao-Minh Lu. Fabrication de CMOS à basse température pour l'intégration 3D séquentielle. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes, 2017. Français. ⟨NNT : 2017GREAT109⟩. ⟨tel-01824340⟩



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