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X. Phi and C. , 5 GT/s pour les dernières configurations. L'Intel Xeon Phi Coprocessor peut embarquer son propre système d'exploitation, supporte les protocoles de parallélisation MPI 8 et openMP 9 , accepte l'adressage IP. L'intel Xeon Phi Coprocessor peut proposer des configurations jusqu'à 61 coeurs (unité de calcul vectoriel) basés sur l'architecture de la famille des processeurs Intel Pentium, description dans le manuel d'Intel 10 Les processeurs sont cadencés à 1.238 GHz, ce qui n'est pas excessifs mais la performance est dans le nombre de processeurs engravés sur une même puce Intel utilise une gravure à 14 nm, ce qui permet de produire des puces comportant plus de 50 coeurs Chaque coeur physique permet de récupérer et de décoder 4 fils d'instructions simultanément ce qui, pour la configuration la plus lourde, gère jusqu'à 244 fils d'instructions. L'intel Xeon Phi Coprocessor tourne sur un environnement 64 bit, fournit la compatibilité pour l'architecture x86 et supporte les set instructions IEEE 754 11 pour l'arithmétique en virgule flottante. La carte est munit d'un environnement très flexible pour le développement d'applications. Chaque coeur est connecté à un anneau d'interconnexion à travers le protocole Core Ring Interface 12 (cf. schéma de l'architecture sur la figure 5.2), qui comprend le cache L2 de 512 Kb. Cette interface permet d'exécuter 2 instructions par cycle, sur le U-pipe (détails dans le manuel d'Intel cité pr´éc´édemmentpr´pr´écpr´éc´pr´éc´édemment) et le V-pipe mais certaines ne peuvent pas être exécutées sur cette dernière (comme les instructions vectorielles) Chaque coeur a un support de calcul de haute précision et optimisé pour les fonctions mathématiques i.e. racine carrée, exponentielle, logarithme, puissance, réciproque etc. . . Des fonctions spéciales liées à la gestion de mémoire (scatter, gather et streaming store) sont très efficaces. Les coeurs comprennent les instructions du cache L1 et du data cache (32 Kb pour chacun des caches) Chaque coeur est muni de registres vectoriels de 32 R12 bit. Malheureusement, la carte ne supporte pas les instructions Intel SIMD 13 comme MMX 14, ni les instructions AVX 16 donc la portabilité du code n'est pas direct mais Intel fournit un nouveau set d'instructions vectorielles. Ce set permet d'exécuter des instructions de calcul arithmétique par vecteur de 512 bit, et peut ainsi traiter simultanément 16 flottants en précision simple (SP) ou 8 en double précisions (DP) Chaque opération peut être une combinaison de multiplication et d'addition permettant de traiter 32 SP ou 16 DP par cycle. La plupart des instructions vectorielles a une latence de 4 cycle d'horloge et une cadence d'un cycle. L'architecture Intel Xeon Phi Coprocessor implémente " seulement, La carte n'est pas directement intégrée sur la carte mère, elle est jusqu'à présent seulement disponible à travers un port PCI 6 mais il offre une bande passante très large de 353 Gb/s consommant 300 watt pour 32 Go de capacité de mémoire type GDDR5 7 avec un pic de vitesse àe 5, 2015.

, disponible à l'adresse suivante: https://ftp.utcluj.ro/ pub/docs/publicatii/intel/pentiumII.pdf 11 Norme de représentation pour les nombres à virgule flottante en binaire. 12 Voir les documentations détaillées dans Chrysos [43], Jeffers [102] et Reed [161]. 13 Single instruction multiple data. Voir https://software.intel.com/sites, Pentium II Processor Developer's Manual 14 Multiple Math eXtension, 1997.

, Mise en place de directive pour tenter l'auto vectorisation du code par le compilateur OpenCL

, Ajout de fonction intrinsèques pour une vectorisation effective

, Utilisation de Vtune 40 pour trouver les noeuds critiques de l'application et ajout du parallélisme dynamique des processus logiques

, Réarrangement des données afin de linéariser l'accès en mémoire et quelques optimisations de fonctions mathématiques

, On peut voir que les optimisations sur le code n'ont pas le même impact en fonction de l'architecture

, optimisation 3 a été faite sur un code qui possède déjà l'optimisation 1 et 2. Il faut noter que la nature des compilateurs jouent un rôle important dans les performances de calcul des codes générés. Entre un compilateur Open Source GNU et celui d'Intel, Les optimisations ne sont pas indépendantes des autres

B. Appendix, Semi-Smooth Newton Method Such a property which is satisfied by F (x) = max{0, x} for instance with G(x) = max{0

K. Itô, suggested to apply the idea to (B.2) reformulated as a(u, v) ? (?, v) = (f, v) ?v ? H 1

, The last equality is equivalent to ? ? 0, ? ? ? + c(u ? ?) i.e. u ? ?, ? ? 0, with equality on one of them for each S. This problem is equivalent to (B.2) for a real

, Algorithm Newton's algorithm 9 applied to (B.3) gives

, Algorithm 9 Semi-Smooth Newton algorithm 1: Choose c > 0, u0, ?0, set k = 0. 2: Determine A k, )) < 0} 3: Set u k+1 = arg min u?H 1 (R + ) { 1

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