M. Abramovici and P. Bradley, Integrated circuit security, Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research Cyber Security and Information Intelligence Challenges and Strategies, CSIIRW '09, p.55, 2009.
DOI : 10.1145/1558607.1558671

S. Adee, The Hunt For The Kill Switch, IEEE Spectrum, vol.45, issue.5, pp.34-39, 2008.
DOI : 10.1109/MSPEC.2008.4505310

Y. Alkabani and F. Koushanfar, Designer's hardware trojan horse, Hardware-Oriented Security and Trust, pp.82-83, 2008.

M. Abramovici and P. Levin, Protecting integrated circuits from silicon trojan horses, 2009.

M. Bhunia, D. Abramovici, P. Agrawal, . Bradley, S. Michael et al., Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution, IEEE Design & Test, vol.30, issue.3, pp.6-17, 2013.
DOI : 10.1109/MDT.2012.2196252

M. Banga, S. Michael, and . Hsiao, A region based approach for the identification of hardware Trojans, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.40-47, 2008.
DOI : 10.1109/HST.2008.4559047

M. Banga, S. Michael, and . Hsiao, Trusted RTL: Trojan detection methodology in pre-silicon designs, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.56-59, 2010.
DOI : 10.1109/HST.2010.5513114

[. Bhunia, S. Michael, M. Hsiao, S. Banga, and . Narasimhan, Hardware Trojan Attacks: Threat Analysis and Countermeasures, Proceedings of the IEEE, pp.1229-1247, 2014.
DOI : 10.1109/JPROC.2014.2334493
URL : https://doi.org/10.1109/jproc.2014.2334493

R. Subhra, C. , and S. Bhunia, Security against hardware trojan attacks using key-based design obfuscation, Journal of Electronic Testing, vol.27, issue.6, pp.767-785, 2011.

. Inc and . Chipworks, Semiconductor manufacturing -reverse engineering of semiconductor components, parts and process, 2016.

[. Courbon, P. Loubet-moundi, J. Jacques, A. Fournier, and . Tria, SEMBA: A SEM based acquisition technique for fast invasive Hardware Trojan detection, 2015 European Conference on Circuit Theory and Design (ECCTD), pp.1-4, 2015.
DOI : 10.1109/ECCTD.2015.7300097
URL : https://hal.archives-ouvertes.fr/hal-01163583

R. Subhra-chakraborty, S. Narasimhan, and S. Bhunia, Hardware trojan : Threats and emerging solutions Resilient hardware trojans detection based on path delay measurements, High Level Design Validation and Test Workshop Hardware Oriented Security and Trust, pp.166-171, 2015.

F. Imeson, A. Emtenan, S. Garg, and M. Tripunitara, Securing computer hardware using 3d integrated circuit (ic) technology and split manufacturing for obfuscation, Presented as part of the 22nd USENIX Security Symposium, pp.495-510, 2013.

Y. Jin and Y. Makris, Hardware trojan detection using path delay fingerprint, Hardware-Oriented Security and Trust, pp.51-57, 2008.

T. Samuel, J. King, A. Tucek, C. Cozzie, W. Grier et al., Designing and implementing malicious hardware, LEET, vol.8, pp.1-8, 2008.

A. Jeffrey, . Kash, C. James, . Tsang, R. Daniel et al., Method and apparatus for reverse engineering integrated circuits by monitoring optical emission, US Patent, vol.6496, p.22, 2002.

[. Love, Y. Jin, and Y. Makris, Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition, IEEE Transactions on Information Forensics and Security, vol.7, issue.1, pp.25-40, 2012.
DOI : 10.1109/TIFS.2011.2160627

J. Li and J. Lach, At-speed delay characterization for ic authentication and trojan horse detection, Hardware-Oriented Security and Trust, pp.8-14, 2008.

. Mcintyre, C. Wolff, S. Papachristou, D. Bhunia, and . Weyer, Dynamic evaluation of hardware trust, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.108-111, 2009.
DOI : 10.1109/HST.2009.5224990

X. T. Ngo, Z. Najm, S. Bhasin, S. Guilley, and J. Danger, Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis, Security Proofs for Embedded Systems. PROOFS, 2014.
DOI : 10.1007/978-3-642-33027-8_2

R. Rad, J. Plusquellic, and M. Tehranipoor, Sensitivity analysis to hardware Trojans using power supply transient signals, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.3-7, 2008.
DOI : 10.1109/HST.2008.4559037

H. Salmani and M. Tehranipoor, Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection, IEEE Transactions on Information Forensics and Security, vol.7, issue.1, pp.76-87, 2012.
DOI : 10.1109/TIFS.2011.2164908

H. Salmani, M. Tehranipoor, and J. Plusquellic, A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.112-125, 2012.
DOI : 10.1109/TVLSI.2010.2093547
URL : http://www.ece.unm.edu/~jimp/pubs/TVLSIver5.pdf

M. Tehranipoor, F. Courbon, P. Loubet-moundi, J. Jacques, A. Fournier et al., A Survey of Hardware Trojan Taxonomy and Detection, European Conference on Circuit Theory and Design, pp.10-25, 2010.
DOI : 10.1109/MDT.2010.7
URL : http://aceslab.org/sites/default/files/A Survey of Hardware_0.pdf

. Cwp-+-09-]-rajat-subhra, F. Chakraborty, S. Wolff, C. Paul, S. Papachristou et al., Mero : A statistical approach for hardware trojan detection, Cryptographic Hardware and Embedded Systems-CHES, pp.396-410

Y. Jin and Y. Makris, Hardware trojan detection using path delay fingerprint, Hardware-Oriented Security and Trust, pp.51-57, 2008.

X. Thuy and N. , Prévention et Détection des Chevaux de Troie Matériels Dans les Circuit Intégrés, 2016.

R. Rad, J. Plusquellic, M. Tehranipoor, R. De, . Non et al., Sensitivity analysis to hardware trojans using power supply transient signals In Hardware-Oriented Security and Trust CONDITION11 ? Création des sous-ensembles, version "améliorée Optics-of : Identifying local outliers, European Conference on Principles of Data Mining and Knowledge Discovery, pp.3-7, 1999.

R. Subhra, C. , and S. Bhunia, Security against hardware trojan through a novel application of design obfuscation, Proceedings of the 2009 International Conference on Computer-Aided Design, pp.113-116, 2009.

B. Çakir and S. Malik, Hardware trojan detection for gate-level ics using signal correlation based clustering, Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, pp.471-476, 2015.

S. Dupuis, P. Ba, M. Flottes, G. D. Natale, and B. Rouzeyre, New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.776-781, 2015.
DOI : 10.7873/DATE.2015.1102
URL : https://hal.archives-ouvertes.fr/lirmm-01141619

[. Natale, S. Dupuis, M. Flottes, and B. Rouzeyre, Identification of hardware trojans triggering signals, Workshop on Trustworthy Manufacturing and Utilization of Secure Devices. TRUDEVICE, 2013.
URL : https://hal.archives-ouvertes.fr/lirmm-00991360

I. Exurville, J. Fournier, J. Dutertre, B. Robisson, and A. Tria, Practical measurements of data path delays for IP authentication & integrity verification, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp.1-6, 2013.
DOI : 10.1109/ReCoSoC.2013.6581551
URL : https://hal.archives-ouvertes.fr/emse-01109140

H. Huang, J. Sun, H. Han, Y. Deng, Y. Sun et al., SHRINK, Proceedings of the 19th ACM international conference on Information and knowledge management, CIKM '10, pp.219-228, 2010.
DOI : 10.1145/1871437.1871469

Y. Jin and Y. Makris, Hardware trojan detection using path delay fingerprint, Hardware-Oriented Security and Trust, pp.51-57, 2008.

H. Kriegel, P. Kröger, E. Schubert, and A. Zimek, Interpreting and Unifying Outlier Scores, SDM, pp.13-24, 2011.
DOI : 10.1137/1.9781611972818.2
URL : http://epubs.siam.org/doi/pdf/10.1137/1.9781611972818.2

P. Kitsos, E. Dimitris, J. Simos, . Torres-jimenez, G. Artemios et al., Exciting FPGA cryptographic Trojans using combinatorial testing, 2015 IEEE 26th International Symposium on Software Reliability Engineering (ISSRE), pp.69-76, 2015.
DOI : 10.1109/ISSRE.2015.7381800
URL : http://revistas.uptc.edu.co/revistas/index.php/ingenieria/article/download/5295/4425

N. Lesperance, S. Kulkarni, and K. Cheng, Hardware Trojan detection using exhaustive testing of k-bit subspaces, The 20th Asia and South Pacific Design Automation Conference, pp.755-760, 2015.
DOI : 10.1109/ASPDAC.2015.7059101
URL : http://cadlab.ece.ucsb.edu/sites/default/files/ASPDAC2015.pdf

, Tetramax, 2016.

T. Donald, L. S. Tang, and . Woo, Exhaustive test pattern generation with constant weight vectors, IEEE Transactions on Computers, vol.100, issue.12, pp.1145-1150, 1983.

J. Wang, Classical Multidimensional Scaling, Geometric Structure of High-Dimensional Data and Dimensionality Reduction, pp.115-129, 2012.
DOI : 10.1007/978-3-642-27497-8_6

. W. Inc and . Foundation, Algorithme de dijkstra, 2016.

[. Wolff, C. Papachristou, S. Bhunia, S. Rajat, and . Chakraborty, Towards trojan-free trusted ICs, Proceedings of the conference on Design, automation and test in Europe, DATE '08, pp.1362-1365, 2008.
DOI : 10.1145/1403375.1403703

K. Xiao, M. Abramovici, and P. Bradley, Bisa : Built-in self-authentication for preventing hardware trojan insertion Integrated circuit security : new threats and solutions, Hardware-Oriented Security and Trust Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research : Cyber Security and Information Intelligence Challenges and Strategies, pp.45-50, 2009.

G. Bloom, B. Narahari, R. Simha, and J. Zambreno, Providing secure execution environments with a last line of defense against trojan circuit attacks. computers & security, pp.660-669, 2009.

C. Carlet, A. Daif, J. Danger, S. Guilley, Z. Najm et al., Optimized linear complementary codes implementation for hardware trojan prevention, 2015 European Conference on Circuit Theory and Design (ECCTD), pp.1-4, 2015.
DOI : 10.1109/ECCTD.2015.7300075

[. Hsiao, W. C. Carter, J. W. Thomas, and W. R. Stringfellow, Reliability, Availability, and Serviceability of IBM Computer Systems: A Quarter Century of Progress, IBM Journal of Research and Development, vol.25, issue.5, pp.453-468, 1981.
DOI : 10.1147/rd.255.0453

K. Niraj, S. Jha, and . Wang, Design and synthesis of self-checking vlsi circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.12, issue.6, pp.878-887, 1993.

[. Mitra, R. Nirmal, . Saxena, J. Edward, and . Mccluskey, A design diversity metric and reliability analysis for redundant systems, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.662-671, 1999.
DOI : 10.1109/TEST.1999.805794
URL : http://crc.stanford.edu/crc_papers/CRC-TR-99-4.pdf

T. Ndg-+-15-]-xuan, J. Ngo, S. Danger, Z. Guilley, O. Najm et al., Hardware property checker for run-time hardware trojan detection, European Conference on Circuit Theory and Design, pp.1-4, 2015.

, Jean-Luc Danger, and Zakaria Najm. Encoding the state of integrated circuits : a proactive and reactive protection against hardware trojans horses, Proceedings of the 9th Workshop on Embedded Systems Security, p.7, 2014.

I. Pomeranz, M. Sudhakar, and . Reddy, Concurrent on-line testing of identical circuits through output comparison using non-identical input vectors, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings., pp.469-476, 2004.
DOI : 10.1109/DFTVS.2004.1347872

K. Dhiraj and . Pradhan, Fault-tolerant computer system design, 1996.

C. Ramamoorthy and Y. Han, Reliability Analysis of Systems with Concurrent Error Detection, IEEE Transactions on Computers, vol.24, issue.9, pp.868-878, 1975.
DOI : 10.1109/T-C.1975.224332

L. Ronald, A. Rivest, L. Shamir, and . Adleman, A method for obtaining digital signatures and public-key cryptosystems, Communications of the ACM, vol.21, issue.2, pp.120-126, 1978.

C. Zeng, N. Saxena, J. Edward, and . Mccluskey, Finite state machine synthesis with concurrent error detection, International Test Conference, pp.672-679, 1999.

, il faut noter que des taux d'occupation élevés (au dessus de 90%) peuvent être atteints par notre méthode. Ensuite, il est intéressant de noter que le taux d'occupation final est généralement plus élevé avec un taux d'occupation initial qui n'est pas élevé. En effet plus grand est le taux d'occupation initial

, Le circuit est placé avec un taux d'occupation initial de 75%. Les cellules en jaune sont celles ajoutées par notre outil avec un taux d'occupation, Un layout du circuit s35932 est présenté dans la figure 6.4

S. Bhasin, J. Danger, S. Guilley, X. T. Ngo, and L. Sauvage, Hardware Trojan Horses in Cryptographic IP Cores, 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, pp.15-29, 2013.
DOI : 10.1109/FDTC.2013.15
URL : https://hal.archives-ouvertes.fr/hal-00855146

M. Banga, S. Michael, and . Hsiao, VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.104-107, 2009.
DOI : 10.1109/HST.2009.5224960

W. Danesh, J. Dofe, and Q. Yu, Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic, VLSI Design, vol.29, issue.5, 2014.
DOI : 10.1109/TIFS.2010.2096811

J. Ichimiya, Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization, US Patent, vol.7, p.76756, 2006.

J. Rajendran, O. Sinanoglu, and R. Karri, Regaining Trust in VLSI Design: Design-for-Trust Techniques, Proceedings of the IEEE, pp.1266-1282, 2014.
DOI : 10.1109/JPROC.2014.2332154

K. Tiri and I. Verbauwhede, Place and Route for Secure Standard Cell Design, Smart Card Research and Advanced Applications VI, pp.143-158, 2004.
DOI : 10.1007/1-4020-8147-2_10
URL : https://link.springer.com/content/pdf/10.1007%2F1-4020-8147-2_10.pdf

K. Xiao and M. Tehranipoor, BISA: Built-in self-authentication for preventing hardware Trojan insertion, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.45-50, 2013.
DOI : 10.1109/HST.2013.6581564

C. 7. Prévention-d-'insertion, . De, . Par, . De, and . De, Probabilités avant fusion. (b) Probabilités après fusion

S. Dupuis, P. Ba, G. D. Natale, M. Flottes, and B. Rouzeyre, A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), pp.49-54, 2014.
DOI : 10.1109/IOLTS.2014.6873671
URL : https://hal.archives-ouvertes.fr/lirmm-01025275

T. Hao-xue, S. Moody, X. Li, S. Zhang, and . Ren, Low overhead design for improving hardware trojan detection efficiency, IEEE National Aerospace and Electronics Conference, pp.379-383, 2014.

B. Zhou, W. Zhang, S. Thambipillai, and J. Teo, A low cost acceleration method for hardware trojan detection based on fan-out cone analysis, Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES '14, p.28, 2014.
DOI : 10.1145/2656075.2656077