Scan-Chain Intra-Cell Aware Testing, Scientific Contributions [IJ.1 ] ,
DOI : 10.1109/TETC.2016.2624311
URL : https://hal.archives-ouvertes.fr/lirmm-01430859
Microprocessor Testing: Functional Meets Structural Test, Journal of Circuits, Systems and Computers, vol.26, issue.08 ,
DOI : 10.1016/j.ejor.2005.09.028
URL : https://hal.archives-ouvertes.fr/lirmm-01718578
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ,
DOI : 10.1109/ISVLSI.2016.42
URL : https://hal.archives-ouvertes.fr/lirmm-01446917
An effective approach for functional test programs compaction, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), p.2016 ,
DOI : 10.1109/DDECS.2016.7482466
URL : https://hal.archives-ouvertes.fr/lirmm-01457396
Scan-chain intra-cell defects grading, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ,
DOI : 10.1109/DTIS.2015.7127349
URL : https://hal.archives-ouvertes.fr/lirmm-01272696
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015. ,
DOI : 10.7873/DATE.2015.1031
URL : https://hal.archives-ouvertes.fr/lirmm-01272937
A Comprehensive Evaluation of Functional Programs for Power-Aware Test, 2014 IEEE 23rd North Atlantic Test Workshop ,
DOI : 10.1109/NATW.2014.23
URL : https://hal.archives-ouvertes.fr/lirmm-01248597
Functional Testing Vs Structural Testing, South European Test Seminar (SETS), 2014. ,
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2014. ,
DOI : 10.7873/DATE.2015.1031
URL : https://hal.archives-ouvertes.fr/lirmm-01272937
Exploring the Impact of Functional Test Programs Re-used for At-Speed Testing, IN: Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM), 2016. ,
Cramming more components onto integrated circuits, reprinted from electronics ff, IEEE Solid-State Circuits Society Newsletter, vol.38, issue.115, pp.11433-11468, 1965. ,
DOI : 10.1109/jproc.1998.658762
Device scaling limits of Si MOSFETs and their application dependencies, Proceedings of the IEEE, pp.259-288, 2001. ,
DOI : 10.1109/5.915374
View from the bottom: nanometer technology AC parametric failures - why, where, and how to detect, Proceedings. 16th IEEE Symposium on Computer Arithmetic, pp.267-276, 2003. ,
DOI : 10.1109/DFTVS.2003.1250121
Emerging Nanoelectronics: Life with and after CMOS, Microelectronics Education, pp.159-160, 2004. ,
DOI : 10.1007/978-1-4020-2651-5_26
A Designer's Guide to Built-in Self-test, 2002. ,
Invisible delay quality - SDQM model lights up what could not be seen, IEEE International Conference on Test, 2005., pp.9-1210, 2005. ,
DOI : 10.1109/TEST.2005.1584088
Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits, 2000. ,
High-frequency, at-speed scan testing, IEEE Design Test of Computers, vol.20, issue.5, pp.17-25, 2003. ,
At-Speed Transition Fault Testing With Low Speed Scan Enable, 23rd IEEE VLSI Test Symposium (VTS'05), pp.42-47, 2005. ,
DOI : 10.1109/VTS.2005.31
URL : http://www.cs.umbc.edu/~plusquel/pubs/vts2005_atspeed.pdf
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality, 2008 IEEE International Test Conference, pp.1-10, 2008. ,
DOI : 10.1109/TEST.2008.4700604
Cell-aware Production test results from a 32-nm notebook processor, 2012 IEEE International Test Conference, pp.1-9, 2012. ,
DOI : 10.1109/TEST.2012.6401533
Cell-Aware Test, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.33, issue.9, pp.1396-1409, 2014. ,
DOI : 10.1109/TCAD.2014.2323216
URL : http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6879635
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing, 2011 Sixteenth IEEE European Test Symposium, pp.153-158, 2011. ,
DOI : 10.1109/ETS.2011.21
URL : https://hal.archives-ouvertes.fr/lirmm-00647822
A case study of ir-drop in structured at-speed testing, International Test Conference, 2003. Proceedings. ITC 2003., pp.1098-1104, 2003. ,
DOI : 10.1109/TEST.2003.1271098
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption, Journal of Low Power Electronics, vol.9, issue.2, pp.253-263, 2013. ,
DOI : 10.1166/jolpe.2013.1259
URL : https://hal.archives-ouvertes.fr/lirmm-00934937
Evolutionary optimization: the µgp toolkit: The ugp toolkit, 2011. ,
DOI : 10.1007/978-0-387-09426-7
Automatic test generation for verifying microprocessors, IEEE Potentials, vol.24, issue.1, pp.34-37, 2005. ,
DOI : 10.1109/MP.2005.1405800
Writing testbenches: functional verification of HDL models ,
DOI : 10.1007/978-1-4615-0302-6
OCCOM-efficient computation of observability-based code coverage metrics for functional verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, issue.8, pp.1003-1015, 2001. ,
DOI : 10.1109/43.936381
URL : http://www.caa.lcs.mit.edu/~devadas/pubs/occom-tcad.ps
Microprocessor Software-Based Self-Testing, IEEE Design & Test of Computers, vol.27, issue.3, pp.4-19, 2010. ,
DOI : 10.1109/MDT.2010.5
Effective software-based self-test strategies for on-line periodic testing of embedded processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.88-99, 2005. ,
DOI : 10.1109/DATE.2004.1268907
URL : http://date.eda-online.co.uk/proceedings/papers/2004/date04/pdffiles/05c_1.pdf
Enhanced Test Program Compaction Using Genetic Programming, 2006 IEEE International Conference on Evolutionary Computation, pp.865-870, 2006. ,
DOI : 10.1109/CEC.2006.1688402
On test program compaction, 2015 20th IEEE European Test Symposium (ETS), pp.1-6, 2015. ,
DOI : 10.1109/ETS.2015.7138771
An evolutionary approach for test program compaction, 2015 16th Latin-American Test Symposium (LATS), pp.1-6, 2015. ,
DOI : 10.1109/LATW.2015.7102406
On the Automation of the Test Flow of Complex SoCs, 24th IEEE VLSI Test Symposium, pp.6-171, 2006. ,
DOI : 10.1109/VTS.2006.51
Evolutionary Optimization: the µGP toolkit: The UGP Toolkit, 2011. ,
DOI : 10.1007/978-0-387-09426-7
Power-aware testing and test strategies for low power devices, 2009. ,
DOI : 10.1007/978-1-4419-0928-2
URL : https://hal.archives-ouvertes.fr/lirmm-00820650
RT-Level Deviation-Based Grading of Functional Test Sequences, 2009 27th IEEE VLSI Test Symposium, pp.264-269, 2009. ,
DOI : 10.1109/VTS.2009.12
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage, 2010 IEEE International Test Conference, pp.1-10, 2010. ,
DOI : 10.1109/TEST.2010.5699266
Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length, IEEE Transactions on Computers, vol.61, issue.6, pp.899-904, 2012. ,
DOI : 10.1109/TC.2011.107
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.376-381, 2010. ,
DOI : 10.1109/DDECS.2010.5491748
Launch-on-Shift-Capture Transition Tests, 2008 IEEE International Test Conference, pp.1-9, 2008. ,
DOI : 10.1109/TEST.2008.4700648
Power-Aware Test Pattern Generation for At-Speed LOS Testing, 2011 Asian Test Symposium, pp.506-510, 2011. ,
DOI : 10.1109/ATS.2011.50
URL : https://hal.archives-ouvertes.fr/lirmm-00651917
Systematic defects in deep sub-micron technologies, 2004 International Conferce on Test, pp.290-299, 2004. ,
DOI : 10.1109/TEST.2004.1386963
An intra-cell defect grading tool, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.298-301, 2014. ,
DOI : 10.1109/DDECS.2014.6868814
URL : https://hal.archives-ouvertes.fr/lirmm-01248591
A review of fault models for lsi/vlsi devices, Software & Microsystems, vol.2, issue.2, pp.44-53, 1983. ,
DOI : 10.1049/sm.1983.0016
On the efficiency of the transition fault model for delay faults ICCAD-90, IEEE International Conference on, pp.272-275, 1990. ,
Bridging and Stuck-At Faults, IEEE Transactions on Computers, vol.23, issue.7, pp.720-727, 1974. ,
DOI : 10.1109/T-C.1974.224020
Functional tests for scan chain latches, Proceedings of 1995 IEEE International Test Conference (ITC), pp.606-615, 1995. ,
DOI : 10.1109/TEST.1995.529889
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models, 2014 IEEE 23rd Asian Test Symposium, pp.318-323, 2014. ,
DOI : 10.1109/ATS.2014.58
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs, 2009 International Test Conference, pp.1-10, 2009. ,
DOI : 10.1109/TEST.2009.5355741
Diagnosis of resistive-open and stuck-open defects in digital cmos ics, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.11, pp.1748-1759, 2005. ,
An efficient fault simulation technique for transition faults in non-scan sequential circuits, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.50-55, 2009. ,
DOI : 10.1109/DDECS.2009.5012098
URL : https://hal.archives-ouvertes.fr/lirmm-00371197
Defect-based test: Simulation and diagnosis, pp.19-37, 2014. ,
Tessent Scan and ATPG User's Manual ,