Reliable gold code generators for GPS receivers, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp.1-4, 2015. ,
DOI : 10.1109/MWSCAS.2015.7282164
URL : https://hal.archives-ouvertes.fr/hal-01151895
Reducing the impact of internal upsets inside the correlation process in GPS Receivers, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.1-5, 2015. ,
DOI : 10.1109/DASIP.2015.7367264
URL : https://hal.archives-ouvertes.fr/hal-01211180
Reliable GPS position on an unreliable hardware, 11 th Colloque GDR SoC-SiP, 2016. ,
URL : https://hal.archives-ouvertes.fr/hal-01331034
Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), pp.80-85, 2016. ,
DOI : 10.1109/SiPS.2016.22
URL : https://hal.archives-ouvertes.fr/hal-01391201
Hardware error correction using local syndromes, 2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017. ,
DOI : 10.1109/SiPS.2017.8109995
URL : https://hal.archives-ouvertes.fr/hal-01611117
Demo: Localisation in a faulty digital GPS receiver, 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016. ,
DOI : 10.1109/DASIP.2016.7853824
Demo : Tracking loop of a GPS receiver under noisy hardware, 2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017. ,
FMC XM105 Debug Card User Guide ,
40 Years of Microprocessor Trend Data ,
Comparing Reliability-Redundancy Tradeoffs for Two von Neumann Multiplexing Architectures, IEEE Transactions On Nanotechnology, vol.6, issue.3, pp.265-279, 2007. ,
DOI : 10.1109/TNANO.2007.891504
The Use of Triple-Modular Redundancy to Improve Computer Reliability, IBM Journal of Research and Development, vol.6, issue.2, pp.200-209, 1962. ,
DOI : 10.1147/rd.62.0200
Reliable low-power digital signal processing via reduced precision redundancy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.497-510, 2004. ,
System-level hardware-based protection of memories against soft-errors, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.1222-1225, 2009. ,
DOI : 10.1109/DATE.2009.5090849
URL : https://www.researchgate.net/profile/Yannick_Bonhomme/publication/221341634_System-level_hardware-based_protection_of_memories_against_soft-errors/links/02e7e52442b34d8439000000.pdf
Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.7-8, 2007. ,
DOI : 10.1109/DATE.2007.364538
URL : http://eprints.soton.ac.uk/263240/1/Camera14.pdf
Razor: a low-power pipeline based on circuit-level timing speculation, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), pp.7-18, 2003. ,
DOI : 10.1109/MICRO.2003.1253179
URL : http://www.ece.ucdavis.edu/~akella/270W05/reading/razor timing speculation.pdf
Hardware error correction using local syndromes, 2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017. ,
DOI : 10.1109/SiPS.2017.8109995
URL : https://hal.archives-ouvertes.fr/hal-01611117
Reliable gold code generators for GPS receivers, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp.1-4, 2015. ,
DOI : 10.1109/MWSCAS.2015.7282164
URL : https://hal.archives-ouvertes.fr/hal-01151895
Reducing the impact of internal upsets inside the correlation process in GPS Receivers, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.1-5, 2015. ,
DOI : 10.1109/DASIP.2015.7367264
URL : https://hal.archives-ouvertes.fr/hal-01211180
Reliable NCO carrier generators for GPS receivers, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.1-5, 2015. ,
DOI : 10.1109/DASIP.2015.7367266
URL : https://hal.archives-ouvertes.fr/hal-01211192
Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), pp.80-85, 2016. ,
DOI : 10.1109/SiPS.2016.22
URL : https://hal.archives-ouvertes.fr/hal-01391201
CPU DB, Communications of the ACM, vol.55, issue.4, pp.10-1027, 2012. ,
DOI : 10.1145/2133806.2133822
New strategies for ensuring time and value correctness in dependable realtime systems, 2009. ,
Process Variations and Process-Tolerant Design, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), pp.699-704, 2007. ,
DOI : 10.1109/VLSID.2007.131
Tackling variability and reliability challenges, IEEE Design and Test of Computers, vol.23, issue.6, pp.520-520, 2006. ,
DOI : 10.1109/MDT.2006.156
Intermittent Faults: A Model and a Detection Procedure, IEEE Transactions on Computers, vol.23, issue.7, pp.713-719, 1974. ,
DOI : 10.1109/T-C.1974.224019
Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection, IEEE Transactions on Nuclear Science, vol.55, issue.4, pp.2281-2288, 2008. ,
DOI : 10.1109/TNS.2008.920426
URL : http://www.lume.ufrgs.br/bitstream/10183/27615/1/000684869.pdf
A conceptual framework for system fault tolerance, 1992. ,
DOI : 10.21236/ADA258467
URL : http://www.sei.cmu.edu/pub/documents/92.reports/ps/tr33.92.ps
Gate sizing to radiation harden combinational logic, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.1, pp.155-166, 2006. ,
DOI : 10.1109/TCAD.2005.853696
Impact of CMOS process scaling and SOI on the soft error rates of logic processes, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), pp.73-74, 2001. ,
DOI : 10.1109/VLSIT.2001.934953
A pseudo-dynamic comparator for error detection in fault tolerant architectures, 2012 IEEE 30th VLSI Test Symposium (VTS), pp.50-55, 2012. ,
DOI : 10.1109/VTS.2012.6231079
URL : https://hal.archives-ouvertes.fr/lirmm-00806778
Cost reduction and evaluation of a temporary faults detecting technique, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp.591-598, 2000. ,
DOI : 10.1109/date.2000.840845
URL : https://hal.archives-ouvertes.fr/hal-00229513
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits, 2011 Asian Test Symposium, pp.136-141, 2011. ,
DOI : 10.1109/ATS.2011.89
URL : https://hal.archives-ouvertes.fr/lirmm-00679513
Low-Cost Protection for SER Upsets and Silicon Defects, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 2007. ,
DOI : 10.1109/DATE.2007.364449
URL : http://www.eecs.umich.edu/~valeria/research/publications/DATE07BulletProof.pdf
Probabilistic Logics and the Synthesis of Reliable Organisms From Unreliable Components, Automata Studies, pp.43-98, 1956. ,
DOI : 10.1515/9781400882618-003
An Error Correction Method for Binary and Multiple-Valued Logic, 2011 41st IEEE International Symposium on Multiple-Valued Logic, pp.105-110, 2011. ,
DOI : 10.1109/ISMVL.2011.52
A theory of asynchronous circuits, Proc. International Symposium on the Theory of Switching Part 1, pp.204-243, 1959. ,
Computation on unreliable architecture, 2013. ,
The residue number system, Managing Requirements Knowledge, International Workshop on, vol.0, p.146, 1959. ,
DOI : 10.1145/1457838.1457864
Energy-efficient soft error-tolerant digital signal processing, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003, pp.336-348, 2006. ,
DOI : 10.1109/ACSSC.2003.1292234
Razor: A variability-tolerant design methodology for low power and robust computing, 2009. ,
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance, IEEE Journal of Solid-State Circuits, vol.44, issue.1, pp.32-48, 2009. ,
DOI : 10.1109/JSSC.2008.2007145
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction, IEEE Journal of Solid-State Circuits, vol.48, issue.1, pp.66-81, 2013. ,
DOI : 10.1109/JSSC.2012.2220912
Hardware efficiency versus error probability in unreliable computation, 2011 IEEE Workshop on Signal Processing Systems (SiPS), pp.168-173, 2011. ,
DOI : 10.1109/SiPS.2011.6088969
URL : https://hal.archives-ouvertes.fr/hal-00663410
Automatic-repeat-request error-control schemes, IEEE Communications Magazine, vol.22, issue.12, pp.5-17, 1984. ,
DOI : 10.1109/MCOM.1984.1091865
Coding approaches to fault tolerance in linear dynamic systems Information Theory, IEEE Transactions on, vol.51, issue.1, pp.210-228, 2005. ,
DOI : 10.1109/tit.2004.839491
Official U.S. government information about the Global Positioning System (GPS) and related topics ,
Fundamentals of Global Positioning System Receivers, 2000. ,
DOI : 10.1002/0471712582
Improving the Design of Frequency Lock Loops for GNSS Receivers, IEEE Transactions on Aerospace and Electronic Systems, vol.48, issue.1, pp.850-868, 2012. ,
DOI : 10.1109/TAES.2012.6129674
Design and testing of an intelligent gps tracking loop for noise reduction and high dynamics applications, GNSS, 2010. ,
ZedBoard Zynq-7000 ARM/FPGA SoC Development Board ,
An Introduction to the CORDIC Algorithm https://www.allaboutcircuits.com/technical-articles/ an-introduction-to-the-cordic-algorithm ,