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Theses

Tolerant GPS receiver circuit for electronics errors

Abstract : There is continual motivation to scale down transistors size and to reduce the supply voltage of the circuits. However, by approaching the limits of transistor scaling and operating at a minimal supply voltage, circuit reliability has emerged as a critical concern. Circuits become more and more susceptible to errors due to Process, Voltage and Temperature (PVT) variations. Occurrence of errors can affect the behavior of circuits and generate a permanent system failure. Therefore, it is increasingly important to deal with errors effects in order to keep future devices working properly. The objective of the thesis is to address the reliability in digital systems and introduce new fault tolerant techniques to perform reliable signal processing applications on unreliable hardware. An example of application has been considered in the thesis: the tracking process of GPS receivers. It contains a very interesting set of different signal processing problem with different requirements of reliability: Correlation process, tracking loops (recursive operations), state machine, Gold and carrier generators. Starting from a noiseless GPS receiver, redundant mechanisms have been proposed and added to design a more resilient GPS receiver tolerant to errors. An Application-Specific Integrated Circuit (ASIC) will be designed, based on thesis results, using the 28 nm technology to validate the performances of the proposed techniques performances. During the thesis, an emulation platform was designed to prepare the experimental environment for the ASIC.
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  • HAL Id : tel-01803420, version 1

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Mohamed Mourad Hafidhi. Tolerant GPS receiver circuit for electronics errors. Signal and Image Processing. Université de Bretagne Sud, 2017. English. ⟨NNT : 2017LORIS458⟩. ⟨tel-01803420⟩

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