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Nouveaux paradigmes de capture d’images et traitements associés pour futurs SoC en nœuds CMOS nanométriques

Abstract : The goal of this thesis is to study new image acquisition paradigm in integrated vision circuits to enhance their robustness and scalability using nanometric technologies (such as the 28nm FDSOI) in order to satisfy the imaging constraints imposed by applications such as Internet of Things. In this case, a heterogeneous system-on-chip (SoC) designed in advanced technology would meet the energy consumption constraints. Using standard imagers is not compatible with this requirement because of their excessive power consumption and their architectures non-compatible with 28nm FDSOI technologies. In addition, in these SoC, significant available digital computational resources coupled with new image acquisition modes would allow ultra-low power consumption while providing the ability to implement complex image processing.After a bibliographic study on the state of the art on image acquisition methods and a study on imagers designed with advanced technologies and on low-power applications, it has been shown that it is necessary to quickly digitize light information received by the sensor (i.e. in the pixel). This is why the subject has been oriented towards an event-based vision sensor architecture.The architecture of an event-based image sensor with its associated smart processing has been developed, taking into account technology constraints. In order to define these constraints, a 28nm FDSOI pixel test circuit has been carried out to evaluate the electro-optical response. Each pixel has a different type and size of photodiodes in order to validate the most effective type and size.Two event-based architectures were studied during this thesis in order to fit with the constraints of an implementation in 28nm FDSOI technologies: a "Time-to-first-Spike" (TTFS) architecture with an inhibition system and an architecture called "multi-bus "using the dense interconnections possibilities offered by the technology. These two architectures aim to reduce the data throughput as well as energy consumption.The processing associated to the acquisition have been validated by MATLAB simulations emulating the event acquisition and pre-processing. This vision system therefore extracts a binary map corresponding to the local contrasts using block inhibition mechanism. This processing architecture is based on TTFS pixel (and its inhibition mechanism) with a dedicated pixel schematic. The binary map is extracted in a synchronous manner, thus avoiding hardware addition inherent to an AER (Adress Event Representation) implementation. This binary map can be used for applications such as motion detection, or classification such as histogram of gradient method (HoG). This extracted binary map approaches local binary patterns (LBP), which are frequently used tools in face detection and recognition.A part of this thesis has been dedicated also to the exploration of FDSOI 28nm capabilities in terms of pixel implementation. Notably, by studying pixels using a photodiode under the FDSOI transistor. It has also been developed ten 3 by 3 pixels matrices using 3D integration with LETI technology CoolCube™.
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Submitted on : Monday, May 28, 2018 - 11:12:22 AM
Last modification on : Thursday, June 11, 2020 - 5:04:07 PM
Long-term archiving on: : Wednesday, August 29, 2018 - 1:02:34 PM


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  • HAL Id : tel-01801134, version 1




Camille Dupoiron. Nouveaux paradigmes de capture d’images et traitements associés pour futurs SoC en nœuds CMOS nanométriques. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes, 2017. Français. ⟨NNT : 2017GREAT100⟩. ⟨tel-01801134⟩



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