N. Abel, S. Manz, F. Grull, and U. Kebschull, Increasing Design Changeability Using Dynamic Partial Reconfiguration, IEEE Transactions on Nuclear Science, vol.57, issue.2, pp.602-609, 2010.
DOI : 10.1109/TNS.2009.2037916

A. Cadi, O. Souissi, R. B. Atitallah, N. Belanger, and A. Artiba, Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays, Journal of Intelligent Manufacturing, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01247399

M. Kadi, B. Janssen, and M. Huebner, FGPU : An SIMT-Architecture for FPGAs, Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '16, pp.254-263, 2016.

G. Amato, F. Carrara, F. Falchi, C. Gennaro, and C. Vairo, Car parking occupancy detection using smart camera networks and Deep Learning, 2016 IEEE Symposium on Computers and Communication (ISCC), pp.1212-1217, 2016.
DOI : 10.1109/ISCC.2016.7543901

M. Amiri, F. M. Siddiqui, C. Kelly, R. Woods, K. Rafferty et al., FPGA-Based Soft-Core Processors for Image Processing Applications, Journal of Signal Processing Systems, vol.25, issue.6, pp.139-156, 2017.
DOI : 10.1145/2502081.2502231
URL : http://doi.org/10.1007/s11265-016-1185-7

K. Andryc, M. Merchant, and R. Tessier, FlexGrip: A soft GPGPU for FPGAs, 2013 International Conference on Field-Programmable Technology (FPT), pp.230-237, 2013.
DOI : 10.1109/FPT.2013.6718358

O. Arcas-abella, G. Ndu, N. Sonmez, M. Ghasempour, A. Armejach et al., An empirical evaluation of High-Level Synthesis languages and tools for database acceleration, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-8, 2014.
DOI : 10.1109/FPL.2014.6927484

K. Behrendt and J. Witt, Deep learning lane marker segmentation from automatically generated labels, 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pp.777-782, 2017.
DOI : 10.1109/IROS.2017.8202238

Y. Bi, C. Li, and F. Yang, Very High Level Synthesis for image processing applications, Proceedings of the 10th International Conference on Distributed Smart Camera, ICDSC '16, pp.160-165, 2016.
DOI : 10.1109/ICIP.2005.1530156

M. Bramberger, A. Doblander, A. Maier, B. Rinner, and H. Schwabach, Distributed Embedded Smart Cameras for Surveillance Applications, Computer, vol.39, issue.2, pp.68-75, 2006.
DOI : 10.1109/MC.2006.55
URL : http://www.iti.tugraz.at/download/publications/bramberger06.pdf

V. Brost, F. Yang, and C. Meunier, Flexible VLIW processor based on FPGA for efficient embedded real-time image processing, Journal of Real-Time Image Processing, vol.50, issue.2, pp.47-59, 2014.
DOI : 10.1117/1.3534199
URL : https://hal.archives-ouvertes.fr/hal-00785262

N. Calagar, S. D. Brown, and J. H. Anderson, Source-level debugging for FPGA highlevel synthesis, 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-8, 2014.
DOI : 10.1109/fpl.2014.6927496

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona et al., LegUp, ACM Transactions on Embedded Computing Systems, vol.13, issue.2, pp.241-2427, 2013.
DOI : 10.1145/2514740

J. Chiang and S. Zammattio, Five Ways to Build Flexibility into Industrial Applications with FPGAs

A. Cilardo and L. Gallo, Interplay of Loop Unrolling and Multidimensional Memory Partitioning in HLS, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.163-168, 2015.
DOI : 10.7873/DATE.2015.0798

J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers et al., High-Level Synthesis for FPGAs: From Prototyping to Deployment, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, issue.4, pp.473-491, 2011.
DOI : 10.1109/TCAD.2011.2110592

Y. Cong, J. Yuan, and Y. Tang, Video Anomaly Search in Crowded Scenes via Spatio-Temporal Motion Context, IEEE Transactions on Information Forensics and Security, vol.8, issue.10, pp.1590-1599, 2013.
DOI : 10.1109/TIFS.2013.2272243

P. Cooke, J. Fowers, G. Brown, and G. Stitt, A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications, ACM Transactions on Reconfigurable Technology and Systems, vol.8, issue.1, pp.1-2, 2015.
DOI : 10.1109/ISCAS.2003.1206117

P. Coussy, D. D. Gajski, M. Meredith, and A. Takach, An Introduction to High-Level Synthesis, IEEE Design & Test of Computers, vol.26, issue.4, pp.8-17, 2009.
DOI : 10.1109/MDT.2009.69
URL : https://hal.archives-ouvertes.fr/hal-00447325

K. C. Dey, A. Mishra, and M. Chowdhury, Potential of Intelligent Transportation Systems in Mitigating Adverse Weather Impacts on Road Mobility: A Review, IEEE Transactions on Intelligent Transportation Systems, vol.16, issue.3, pp.1107-1119, 2015.
DOI : 10.1109/TITS.2014.2371455

M. J. Dworkin, SP 800-38A 2001 Edition Recommendation for Block Cipher Modes of Operation : Methods and Techniques, 2001.

F. Erden, S. Velipasalar, A. Z. Alkar, and A. E. Cetin, Sensors in Assisted Living: A survey of signal and image processing methods, IEEE Signal Processing Magazine, vol.33, issue.2, pp.36-44, 2016.
DOI : 10.1109/MSP.2015.2489978

S. Fleck and W. Straßer, Smart Camera Based Monitoring System and Its Application to Assisted Living, Proceedings of the IEEE, pp.1698-1714, 2008.
DOI : 10.1109/JPROC.2008.928765

E. Fossum, CMOS Image Sensors : electronic camera on a chip, Electron Devices Meeting, 1995. IEDM '95., International, pp.17-25, 1995.

L. Gallo, A. Cilardo, D. Thomas, S. Bayliss, and G. A. Constantinides, Area implications of memory partitioning for high-level synthesis on FPGAs, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-4, 2014.
DOI : 10.1109/FPL.2014.6927417

X. Gao and T. Yoshimura, Genetic algorithm based pipeline scheduling in high-level synthesis, 2013 IEEE 10th International Conference on ASIC, pp.1-4, 2013.

J. Goeders and S. J. Wilton, Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.36, issue.1, pp.83-96, 2017.
DOI : 10.1109/TCAD.2016.2565204

J. B. Goeders and S. J. Wilton, VersaPower: Power estimation for diverse FPGA architectures, 2012 International Conference on Field-Programmable Technology, pp.229-234, 2012.
DOI : 10.1109/FPT.2012.6412139

Y. Hara, H. Tomiyama, S. Honda, and H. Takada, Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, pp.242-254, 2009.
DOI : 10.2197/ipsjjip.17.242

M. Hemmati, M. Biglari-abhari, S. Niar, and S. Berber, Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems, Proceedings of the 54th Annual Design Automation Conference 2017 on , DAC '17, pp.1-6, 2017.
DOI : 10.1109/IJCNN.2016.7727715

K. Heyse, T. Davidson, E. Vansteenkiste, K. Bruneel, and D. Stroobandt, Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS, 2013 23rd International Conference on Field programmable Logic and Applications, 2013.
DOI : 10.1109/FPL.2013.6645516

H. Hirschmuller, Improvements in real-time correlation-based stereo vision, Proceedings IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV 2001), pp.141-148, 2001.
DOI : 10.1109/SMBV.2001.988772

E. Homsirikamol and K. Gaj, Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), pp.1-8, 2014.
DOI : 10.1109/ReConFig.2014.7032504

R. Jevtic and C. Carreras, Power Measurement Methodology for FPGA Devices, IEEE Transactions on Instrumentation and Measurement, vol.60, issue.1, pp.237-247, 2011.
DOI : 10.1109/TIM.2010.2047664
URL : http://oa.upm.es/11621/2/INVE_MEM_2011_106085.pdf

W. Jiang, C. Xiao, H. Jin, S. Zhu, and Z. Lu, Vehicle Tracking with Nonoverlapping Views for Multi-camera Surveillance System, 2013 IEEE 10th International Conference on High Performance Computing and Communications, 2013.

M. A. Kadi and M. Huebner, Integer computations with soft GPGPU on FPGAs, 2016 International Conference on Field-Programmable Technology (FPT), pp.28-35, 2016.

R. Kalarot and J. Morris, Comparison of FPGA and GPU implementations of realtime stereo vision, 2010 IEEE Computer Society Conference on Computer Vision and Pattern Recognition -Workshops, pp.9-15, 2010.

B. Kienhuis, E. F. Deprettere, P. Wolf, and K. A. Vissers, A Methodology to Design Programmable Embedded Systems -The Y-Chart Approach, Embedded Processor Design Challenges : Systems, Architectures, Modeling, and Simulation -SAMOS, pp.18-37, 2002.

A. Kulkarni, D. Stroobandt, A. Werner, F. Fricke, and M. Hübner, Pixie : A heterogeneous virtual coarse-grained reconfigurable array for high performance image processing applications, 1705.

A. Lakshminarayana, S. Ahuja, and S. Shukla, High Level Power Estimation Models for FPGAs, 2011 IEEE Computer Society Annual Symposium on VLSI, pp.7-12, 2011.
DOI : 10.1109/ISVLSI.2011.79

J. Lapalme, B. Theelen, N. Stoimenov, J. Voeten, L. Thiele et al., Ychart based system design : a discussion on approaches, 2009.

Y. Lecun, Y. Bengio, and G. Hinton, Deep learning, Nature, vol.9, issue.7553, pp.436-444, 2015.
DOI : 10.1007/s10994-013-5335-x

F. Li, D. Chen, L. He, and J. Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays , FPGA '03, pp.175-184, 2003.
DOI : 10.1145/611817.611844
URL : http://ballade.cs.ucla.edu/~cong/papers/7_1.PDF

H. Li, S. Katkoori, and W. Mak, Power minimization algorithms for LUT-based FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems, vol.9, issue.1, pp.33-51, 2004.
DOI : 10.1145/966137.966139
URL : http://www.cs.unt.edu/~hli/publications/p33-li.pdf

P. Li, Y. Wang, P. Zhang, G. Luo, T. Wang et al., Memory partitioning and scheduling co-optimization in behavioral synthesis, Proceedings of the International Conference on Computer-Aided Design, ICCAD '12, pp.488-495, 2012.
DOI : 10.1145/2429384.2429484

G. Liu, M. Tan, S. Dai, R. Zhao, and Z. Zhang, Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.36, issue.11, pp.1817-1830, 2017.
DOI : 10.1109/TCAD.2017.2664067

H. Liu and L. P. Carloni, On learning-based methods for design-space exploration with high-level synthesis, Proceedings of the 50th Annual Design Automation Conference on, DAC '13, pp.1-7, 2013.
DOI : 10.1145/2463209.2488795

J. Liu, J. Wickerson, and G. A. Constantinides, Loop Splitting for Efficient Pipelining in High-Level Synthesis, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.72-79, 2016.
DOI : 10.1109/FCCM.2016.27

C. Lo and P. Chow, Model-based optimization of High Level Synthesis directives, 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp.1-10, 2016.
DOI : 10.1109/FPL.2016.7577358

A. Mahapatra and B. C. Schafer, Machine-learning based simulated annealer method for high level synthesis design space exploration, Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn), pp.1-6, 2014.
DOI : 10.1109/ESLsyn.2014.6850383

H. Makhijani and S. Meier, A high level design solution for FPGA's, Proceedings of WESCON '94, pp.596-603, 1994.
DOI : 10.1109/WESCON.1994.403530

G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, vol.26, issue.4, pp.18-25, 2009.
DOI : 10.1109/MDT.2009.83

. Mathworks, HDL Coder User's Guide, 2016.

M. Mattavelli, I. Amer, and M. Raulet, The Reconfigurable Video Coding Standard [Standards in a Nutshell, IEEE Signal Processing Magazine, vol.27, issue.3, pp.159-167, 2010.
DOI : 10.1109/MSP.2010.936032
URL : https://hal.archives-ouvertes.fr/hal-00488661

M. Mcdonnell, Box-filtering techniques, Computer Graphics and Image Processing, vol.17, issue.1, pp.65-70, 1981.
DOI : 10.1016/S0146-664X(81)80009-3

W. Meeus, K. Van-beeck, T. Goedemé, J. Meel, and D. Stroobandt, An overview of today's high-level synthesis tools. Design Automation for Embedded Systems, pp.31-51, 2012.

D. Meidanis, K. Georgopoulos, and I. Papaefstathiou, FPGA power consumption measurements and estimations under different implementation parameters, 2011 International Conference on Field-Programmable Technology, pp.1-6, 2011.
DOI : 10.1109/FPT.2011.6132694

M. Munz, M. Mahlisch, and K. Dietmayer, Generic Centralized Multi Sensor Data Fusion Based on Probabilistic Sensor and Environment Models for Driver Assistance Systems, IEEE Intelligent Transportation Systems Magazine, vol.2, issue.1, pp.6-17, 2010.
DOI : 10.1109/MITS.2010.937293

R. Nane, V. M. Sima, B. Olivier, R. Meeuws, Y. Yankova et al., DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler, 22nd International Conference on Field Programmable Logic and Applications (FPL), pp.619-622, 2012.
DOI : 10.1109/FPL.2012.6339221

D. Navarro, L. A. Luc?a, I. Barragán, and . Urriza, High-Level Synthesis for Accelerating the FPGA Implementation of Computationally Demanding Control Algorithms for Power Converters, IEEE Transactions on Industrial Informatics, vol.9, issue.3, pp.1371-1379, 2013.
DOI : 10.1109/TII.2013.2239302

D. J. Pagliari, M. R. Casu, and L. P. Carloni, Accelerators for Breast Cancer Detection, ACM Transactions on Embedded Computing Systems, vol.16, issue.3
DOI : 10.1016/j.jpdc.2011.10.013

M. Pelcat, C. Bourrasset, L. Maggiani, and F. Berry, Design productivity of a high level synthesis compiler versus HDL, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp.140-147, 2016.
DOI : 10.1109/SAMOS.2016.7818341
URL : https://hal.archives-ouvertes.fr/hal-01358210

N. K. Pham, A. K. Singh, A. Kumar, and M. M. Khin, Exploiting Loop-Array Dependencies to Accelerate the Design Space Exploration with High Level Synthesis, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.157-162, 2015.
DOI : 10.7873/DATE.2015.0199

C. Pilato and F. Ferrandi, Bambu: A modular framework for the high level synthesis of memory-intensive applications, 2013 23rd International Conference on Field programmable Logic and Applications, pp.1-4, 2013.
DOI : 10.1109/FPL.2013.6645550

K. K. Poon, S. J. Wilton, and A. Yan, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems, vol.10, issue.2, pp.279-302, 2005.
DOI : 10.1145/1059876.1059881

A. Prost-boucle, O. Muller, and F. Rousseau, Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints, Journal of Systems Architecture, vol.60, issue.1, pp.79-93, 2014.
DOI : 10.1016/j.sysarc.2013.10.002
URL : https://hal.archives-ouvertes.fr/hal-00914536

B. Rinner and W. Wolf, An Introduction to Distributed Smart Cameras, Proceedings of the IEEE, pp.1565-1575, 2008.
DOI : 10.1109/JPROC.2008.928742

M. Ruiz, G. Sutter, S. Lopez-buedo, J. Ramos, J. E. De et al., Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp.1-6, 2015.
DOI : 10.1109/ReConFig.2015.7393325

B. C. Schafer, Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35, issue.3, pp.394-406, 2016.
DOI : 10.1109/TCAD.2015.2472007

B. C. Schafer, Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.36, issue.1, pp.97-105, 2017.
DOI : 10.1109/TCAD.2016.2550501

D. Scharstein and R. Szeliski, A taxonomy and evaluation of dense two-frame stereo correspondence algorithms, Proceedings IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV 2001), pp.7-42, 2002.
DOI : 10.1109/SMBV.2001.988771

M. Schmid, N. Apelt, F. Hannig, and J. Teich, An image processing library for C-based high-level synthesis, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-4, 2014.
DOI : 10.1109/FPL.2014.6927424

M. Schmid, O. Reiche, F. Hannig, and J. Teich, Loop coarsening in C-based High-Level Synthesis, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.166-173, 2015.
DOI : 10.1109/ASAP.2015.7245730

A. Sengupta and R. Sedaghat, Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration, 2011 12th International Symposium on Quality Electronic Design, pp.1-9, 2011.
DOI : 10.1109/ISQED.2011.5770772

A. Severance and G. G. Lemieux, Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
DOI : 10.1109/CODES-ISSS.2013.6658993

L. Shang, A. S. Kaviani, and K. Bathala, Dynamic power consumption in Virtex???-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, pp.157-164, 2002.
DOI : 10.1145/503048.503072

D. Sharma, V. Dumitriu, and L. Kirischian, Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power, pp.177-186, 2017.
DOI : 10.1109/ClusterW.2012.41

F. M. Siddiqui, M. Russell, B. Bardak, R. Woods, and K. Rafferty, IPPro: FPGA based image processing processor, 2014 IEEE Workshop on Signal Processing Systems (SiPS), pp.1-6, 2014.
DOI : 10.1109/SiPS.2014.6986057
URL : https://pure.qub.ac.uk/portal/files/12692968/PID3359731.pdf

H. Sim, A. Rahman, and J. Lee, Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.2799-2802, 2016.
DOI : 10.1109/TVLSI.2016.2520491

K. C. Smith, L. C. Wang, and . Fujino, Through the Looking Glass: Trend Tracking for ISSCC 2012, IEEE Solid-State Circuits Magazine, vol.4, issue.1, pp.4-20, 2012.
DOI : 10.1109/MSSC.2011.2177577

R. Solomon, P. A. Sandborn, and M. G. Pecht, Electronic part life cycle concepts and obsolescence forecasting, IEEE Transactions on Components and Packaging Technologies, vol.23, issue.4, pp.707-717, 2000.

C. L. Sotiropoulou, S. Gkaitatzis, A. Annovi, M. Beretta, P. Giannetti et al., A Multi-Core FPGA-Based 2D-Clustering Implementation for Real-Time Image Processing, IEEE Transactions on Nuclear Science, vol.61, issue.6, pp.613599-3606, 2014.
DOI : 10.1109/TNS.2014.2364183

F. Sun, H. Wang, F. Fu, and X. Li, Survey of FPGA low power design, 2010 International Conference on Intelligent Control and Information Processing, 2010.
DOI : 10.1109/ICICIP.2010.5565246

X. Tang, P. E. Gaillardon, and G. D. Micheli, FPGA-SPICE: A simulation-based power estimation framework for FPGAs, 2015 33rd IEEE International Conference on Computer Design (ICCD), pp.696-703, 2015.
DOI : 10.1109/ICCD.2015.7357183

D. B. Thomas, Synthesisable recursion for C++ HLS tools, 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.91-98, 2016.
DOI : 10.1109/ASAP.2016.7760777

T. Tziortzios and S. Dokouzyannis, High throughput and energy efficient two-dimensional inverse discrete cosine transform architecture, IET Image Processing, vol.7, issue.5, pp.533-541, 2013.
DOI : 10.1049/iet-ipr.2012.0671

J. Villarreal, A. Park, W. Najjar, and R. Halstead, Designing Modular Hardware Accelerators in C with ROCCC 2.0, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.127-134, 2010.
DOI : 10.1109/FCCM.2010.28

S. Vishwakarma and A. Agrawal, A survey on activity recognition and behavior understanding in video surveillance, The Visual Computer, vol.114, issue.12, pp.983-1009, 2013.
DOI : 10.1016/j.cviu.2009.11.005

V. Viswanathan, A Scalable Flexible and Dynamic Reconfigurable Architecture for High Performance Embedded Computing, 2015.

Y. Wang, P. Li, and J. Cong, Theory and algorithm for generalized memory partitioning in high-level synthesis, Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays, FPGA '14, pp.199-208, 2014.
DOI : 10.1145/2554688.2554780

C. D. Ward and C. W. Sohns, Electronic component obsolescence, IEEE Instrumentation & Measurement Magazine, vol.14, issue.6, pp.8-12, 2011.
DOI : 10.1109/MIM.2011.6086892

. Najjar, High-level language tools for reconfigurable computing, Proceedings of the IEEE, pp.390-408, 2015.

. Xilinx, A Simple Method of Estimating Power in XC4000XL

. Xilinx, ZC706 Evaluation Board for the Zynq-7000 XC7Z045 All Programmable SoC User Guide

. Xilinx, LogiCORE IP Color Filter Array Interpolation v3, 2010.

. Xilinx, UG902 Vivado Design Suite User Guide High-Level Synthesis, 2015.

Z. Xue and D. B. Thomas, SynADT: Dynamic Data Structures in High Level Synthesis, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.64-71, 2016.
DOI : 10.1109/FCCM.2016.26

J. Yan, J. Yuan, P. H. Leong, W. Luk, and L. Wang, Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.252842-2855, 2017.
DOI : 10.1109/TVLSI.2017.2713527

P. Yiannacouras, J. G. Steffan, and J. Rose, Portable, Flexible, and Scalable Soft Vector Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1429-1442, 2012.
DOI : 10.1109/TVLSI.2011.2160463
URL : http://www.eecg.toronto.edu/~jayar/pubs/yiannacouras/yiannacourastvlsi12.pdf

J. Yudi, C. H. Llanos, and M. Huebner, System-level design space identification for Many-Core Vision Processors, Microprocessors and Microsystems, vol.52, issue.2, p.52
DOI : 10.1016/j.micpro.2017.05.013

M. Zab?ocki, K. Go?ciewska, D. Frejlichowski, and R. Hofman, Intelligent video surveillance systems for public spaces ? a survey, Journal of Theoretical and Applied Computer Science, vol.8, pp.13-27, 2014.

J. Zhang, F. Y. Wang, K. Wang, W. H. Lin, X. Xu et al., Data-Driven Intelligent Transportation Systems: A Survey, IEEE Transactions on Intelligent Transportation Systems, vol.12, issue.4, pp.1624-1639, 2011.
DOI : 10.1109/TITS.2011.2158001

G. Zhong, A. Prakash, Y. Liang, T. Mitra, and S. Niar, Lin-analyzer, Proceedings of the 53rd Annual Design Automation Conference on, DAC '16, pp.1-6, 2016.
DOI : 10.1109/ICCD.2014.6974719