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Fabrication and Characterization of Gate-All-Around Stacked-Nanowire/Nanosheet MOS transistors realized by a Gate-Last approach for sub-7 nm technology nodes.

Abstract : The future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport.
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https://tel.archives-ouvertes.fr/tel-01780190
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Submitted on : Friday, April 27, 2018 - 11:42:09 AM
Last modification on : Tuesday, October 6, 2020 - 8:38:03 AM

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GABEN_2017_diffusion.pdf
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  • HAL Id : tel-01780190, version 1

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Loic Gaben. Fabrication and Characterization of Gate-All-Around Stacked-Nanowire/Nanosheet MOS transistors realized by a Gate-Last approach for sub-7 nm technology nodes.. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2017. English. ⟨NNT : 2017GREAT095⟩. ⟨tel-01780190⟩

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