Contribution à l'amélioration des plateformes virtuelles SystemC/TLM : configuration, communication et parallélisme

Abstract : The market for Internet Of Things (IOT) is on the rise. It is predicted to continue to grow at a sustained pace in the coming years. Connected objects are composed of dedicated electronic components, processors and software. The design of such systems is today a challenge from an industrial point of view. This challenge is reinforced by market competition and time tomarket that directly impact the success of a system. In a current design process involvesthe development of a specification. Initially, the team in charge of hardware development beginsto design the system. Second, the application part can be done by software developers. Oncethe first hardware prototype is available, the software team can then integrate their part and try tovalidate the functionality. This step may reveal defects in the software but also in the hardware architecture. Unfortunately, the discovery of these errors occurs far too late in the design process,could impacts the marketing of the system and potentially its success. In order to ensure that the hardware and software designs will work together as early as possible, methodologies based onthe SystemC / Transaction Level Modeling (TLM) standard have been widely adopted. They involvethe modelling and simulation of the proposed hardware architectures. During the initial phasesof a product’s design, they enable the software and hardware team to share a virtual version ofthe (future) system. This virtual version is more commonly referred to as a virtual platform. It facilitates early software development, test and validation; reduces material cost by limiting the number of prototypes; saves time and money by reducing risks. However, connected objects are increasingly incorporating hardware and software features. As the requirements have evolved, theSystemC / TLM simulation standard no longer meets all expectations. It includes aspects related to the simulation of systems composed of many functionality, disparate communication protocolsbut also complex and time consuming models during the simulation. Some works have already been carried out on these subjects. However, as the number of components increases, all formsof interoperability of models and tools become increasingly difficult to handle. Moreover, mostof the research has resulted in solutions that are not inter-operable and can not reuse existingmodels. To solve these problems, this thesis proposes a solution for configuring SystemC / TLMmodels. It is now part of the standard Configuration, Control and Inspection (CCI). In a secondstep, the modeling of high-level abstraction communication protocols (TLM Loosely Timed (LT)and Approximately Timed (AT)) has been studied, as it relates to non-bus protocols. An evolution of the standard to improve support, interoperability and reuse is also proposed. In a third step,a change of the SystemC standard and more precisely of the behavior of the simulation kernelhas been studied to support asynchronous events. These open the way to parallelization and distribution of models on different threads / machines. In a fourth step, a solution to integrate Central Processing Units (CPU) models integrated in Quick EMUlator (QEMU), a system emulator/ virtualizer, has been studied. Finally, all these contributions have been applied in the modeling ofa set of objects connected to a gateway.
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Guillaume Delbergue. Contribution à l'amélioration des plateformes virtuelles SystemC/TLM : configuration, communication et parallélisme. Electronique. Université de Bordeaux, 2017. Français. ⟨NNT : 2017BORD0916⟩. ⟨tel-01778172⟩

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