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Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures

Abstract : The technological evolution and the always increasing application performance demand have made of many-core architectures the necessary new trend in processor design. These architectures are composed of a large number of processing resources (hundreds or more) providing massive parallelism and high performance. Indeed, many-core architectures allow a wide number of applications coming from different sources, with a different level of sensitivity and trust, to be executed in parallel sharing physical resources such as computation, memory and communication infrastructure. However, this resource sharing introduces important security vulnerabilities. In particular, sensitive applications sharing cache memory with potentially malicious applications are vulnerable to logical cache-based side-channel attacks. These attacks allow an unprivileged application to access sensitive information manipulated by other applications despite partitioning methods such as memory protection and virtualization. While a lot of efforts on countering these attacks on multi-core architectures have been done, these have not been designed for recently emerged many-core architectures and require to be evaluated, and/or revisited in order to be practical for these new technologies. In this thesis work, we propose to enhance the operating system services with security-aware application deployment and resource allocation mechanisms in order to protect sensitive applications against cached-based attacks. Different application deployment strategies allowing spatial isolation are proposed and compared in terms of several performance indicators. Our proposal is evaluated through virtual prototyping based on SystemC and Open Virtual Platforms(OVP) technology.
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Submitted on : Wednesday, April 25, 2018 - 3:10:06 PM
Last modification on : Wednesday, October 14, 2020 - 4:09:28 AM


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  • HAL Id : tel-01777699, version 2


Maria Méndez Real. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures. Cryptography and Security [cs.CR]. Université de Bretagne Sud, 2017. English. ⟨NNT : 2017LORIS454⟩. ⟨tel-01777699v2⟩



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