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Etude d’une lithographie ligne/espace innovante par auto-assemblage dirigé d’un copolymère à blocs pour la réalisation de dispositifs CMOS sub-20nm

Abstract : There is a fixed limit to the maximum resolution the photolithography can provide in the context of the integrated circuit’s size reduction encouraged by the microelectronic industry. The Directed Self-Assembly (DSA) of bloc copolymers (BCP) can be used as a complementary technique enabling smaller critical dimensions of features (CD) obtained by density multiplication of initial, loose i193 lithography patterns. These materials can undergo specific phase separation to self-assemble into periodic, sub-20nm ordered nanostructures.Fast, cost-efficient and highly compatible with equipment and techniques already in use in the industry for line/space (L/S) applications, the different DSA processes found in literature still suffer from defectivity, roughness and CD uniformity (CDU) issues. Most successful solutions are made possible at the loss of some of the most appealing DSA features, mainly its compatibility with current i193 lithography. In this context, the work of this thesis studied and proposed innovative solutions to the problematics posed when using graphoepitaxy as the DSA complementary technique.This work presented therein - revolving around a 38nm period lamellar PS-b-PMMA material - first tried to comprehend the mechanisms involved in the self-assembly of lamellae in one of two environment: flat configuration and 3D, graphoepitaxy configuration. In the former, a study of the parameters dictating the morphology, orientation and defect levels of the BCP was performed. This provides a mean to optimize the kinetics of self-assembly to last less than five minutes while enabling stable and reproducible morphology. Materials optimization and atmosphere composition’s impact during annealing is also discussed. This initial knowledge is then used to perform the density multiplication of L/S guiding pattern using conventional optical lithography at Leti. The study of the lamellae morphology as a function of the multiples guiding patterns’ parameters (CD, interface chemistries, thickness levels…) provides fixed process windows (PW) for a stable process over a 300mm wafer. The shape and size of these PWs is further confirmed by a statistic study of defectivity and roughness metrics as defined by a specific metrology protocol developed during this thesis. This work has led to the publication of a paper.In an effort to demonstrate its relevance in the industry, full integration of this DSA process is carried out in pursuit of functional stacked nanowire (NW) transistors acquisition. First etching tests failed though, as they revealed unknown defective formation of the lamellae at the buried interface. The etching process Leti available at Leti proved enable to compensate for these local variations of transfer features. Consequently, a new iteration of the DSA process is presented. It consists in using UV light exposure to selectively shift the interfacial energies of the guiding patterns’ surfaces. A study of the shift in both the observed lamellae morphology and the composition of the material (followed by Infrared Spectroscopy) as a function of the UV dosage is performed. It identifies a photo-oxidation mechanism which can be finely tuned to independently promote defect-free alignment of the BCP lamellae with any of the guiding pattern surfaces. This work, currently awaiting publication, is further verified by the different etching steps achieving monocrystalline silicon nanowires of controlled dimensions. The associated transistors are now being submitted to electrical characterization. Full wafer uniformity of features is a work in progress however, as BCP thickness filling of guiding patterns is still highly dependent on their density.
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  • HAL Id : tel-01772011, version 1

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Guillaume Claveau. Etude d’une lithographie ligne/espace innovante par auto-assemblage dirigé d’un copolymère à blocs pour la réalisation de dispositifs CMOS sub-20nm. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes, 2017. Français. ⟨NNT : 2017GREAT091⟩. ⟨tel-01772011⟩

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