N. Agarwal, T. Krishna, L. S. Peh, and N. K. Jha, GARNET: A detailed on-chip network model inside a full-system simulator, 2009 IEEE International Symposium on Performance Analysis of Systems and Software, pp.33-42, 2009.
DOI : 10.1109/ISPASS.2009.4919636

S. Akbari, A. Shafiee, M. Fathy, and R. Berangi, AFRA: A low cost high performance reliable routing for 3D mesh NoCs, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.332-337, 2012.
DOI : 10.1109/DATE.2012.6176490

D. Avresky, F. Chaix, and M. Nicolaidis, Congestion-Aware Adaptive Routing in 2D-Mesh Multicores, 2014 IEEE 13th International Symposium on Network Computing and Applications, pp.50-58, 2014.
DOI : 10.1109/NCA.2014.13

URL : https://hal.archives-ouvertes.fr/hal-01412543

M. Bahmani, A. Sheibanyrad, F. Pétrot, F. Dubois, D. et al., A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies, 2012 IEEE Computer Society Annual Symposium on VLSI, pp.9-14, 2012.
DOI : 10.1109/ISVLSI.2012.19

URL : https://hal.archives-ouvertes.fr/hal-00745456

A. Bakhoda, J. Kim, and T. M. Aamodt, Throughput-Effective On-Chip Networks for Manycore Accelerators, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp.421-432, 2010.
DOI : 10.1109/MICRO.2010.50

A. Bartzas, N. Skalis, K. Siozios, and D. Soudris, Exploration of alternative topologies for application-specific 3d networks-on-chip, Proc. of WASP, p.43, 2007.

D. U. Becker and W. J. Dally, Allocator implementations for network-on-chip routers, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09, pp.1-12, 2009.
DOI : 10.1145/1654059.1654112

L. Benini, 3d-mpsocs: architectural and design technology outlook, Keynote presentation at 7th International Forum on ApplicationSpecific MultiProcessor SoC. 5, pp.43-142, 2008.

R. V. Boppana and S. Chalasani, A framework for designing deadlock-free wormhole routing algorithms, IEEE Transactions on Parallel and Distributed Systems, vol.7, issue.2, pp.169-183, 1996.
DOI : 10.1109/71.485506

V. Catania, A. Mineo, S. Monteleone, M. Palesi, P. et al., Noxim: An open, extensible and cycle-accurate network on chip simulator, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015.
DOI : 10.1109/ASAP.2015.7245728

F. Chaix, D. Avresky, N. E. Zergainoh, and M. Nicolaidis, Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems, 2010 Ninth IEEE International Symposium on Network Computing and Applications, pp.52-59, 2010.
DOI : 10.1109/NCA.2010.14

URL : https://hal.archives-ouvertes.fr/hal-00544568

F. Chaix, D. Avresky, N. Zergainoh, and M. Nicolaidis, A fault-tolerant deadlockfree adaptive routing for on chip interconnects, Design, Automation & Test in Europe, pp.1-4, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00671500

A. Charif, A. Coelho, N. E. Zergainoh, and M. Nicolaidis, Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.672-677, 2017.
DOI : 10.1109/ASPDAC.2017.7858401

URL : https://hal.archives-ouvertes.fr/hal-01523898

A. Charif, A. Coelho, N. Zergainoh, and M. Nicolaidis, MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips, 2017 18th IEEE Latin American Test Symposium (LATS), pp.1-4, 2017.
DOI : 10.1109/LATW.2017.7906769

URL : https://hal.archives-ouvertes.fr/hal-01523899

A. Charif, N. Zergainoh, A. Coelho, and M. Nicolaidis, Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs, 2017 22nd IEEE European Test Symposium (ETS), pp.1-6, 2017.
DOI : 10.1109/ETS.2017.7968219

URL : https://hal.archives-ouvertes.fr/hal-01523897

A. Charif, N. Zergainoh, and M. Nicolaidis, A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.121-126, 2016.
DOI : 10.1109/DFT.2016.7684082

URL : https://hal.archives-ouvertes.fr/hal-01445867

W. Dally, Virtual-channel flow control, Proceedings. The 17th Annual International Symposium on Computer Architecture, pp.60-68, 1990.

W. J. Dally, Virtual-channel flow control, IEEE Transactions on Parallel and Dis- BIBLIOGRAPHY, vol.143, 1992.

W. J. Dally and H. Aoki, Deadlock-free adaptive routing in multicomputer networks using virtual channels, IEEE Transactions on Parallel and Distributed Systems, vol.4, issue.4, pp.466-475, 1993.
DOI : 10.1109/71.219761

W. J. Dally and C. L. Seitz, Deadlock-Free Message Routing in Multiprocessor Interconnection Networks, IEEE Transactions on Computers, vol.36, issue.5, p.15, 1988.
DOI : 10.1109/TC.1987.1676939

W. J. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), pp.684-689, 2001.
DOI : 10.1109/DAC.2001.935594

W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua et al., Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design and Test of Computers, vol.22, issue.6, pp.498-510, 2005.
DOI : 10.1109/MDT.2005.136

M. Dimopoulos, Y. Gang, L. Anghel, M. Benabdenbi, N. Zergainoh et al., Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip, Microprocessors and Microsystems, vol.38, issue.6, pp.38620-635, 2014.
DOI : 10.1016/j.micpro.2014.04.003

URL : https://hal.archives-ouvertes.fr/hal-01142543

J. Duato, A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.10, pp.1055-1067, 1995.
DOI : 10.1109/71.473515

J. Duato, A theory of fault-tolerant routing in wormhole networks, IEEE Transactions on Parallel and Distributed Systems, vol.8, issue.8, pp.790-802, 1997.
DOI : 10.1109/71.605766

F. Dubois, A. Sheibanyrad, F. Petrot, and M. Bahmani, Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs, IEEE Transactions on Computers, vol.62, issue.3, pp.609-615, 2013.
DOI : 10.1109/TC.2011.239

URL : https://hal.archives-ouvertes.fr/hal-01138285

. Dyxyz, Fully adaptive routing algorithm for 3D NoCs, Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013, pp.499-503

M. Ebrahimi and M. Daneshtalab, EbDa, ISCA, pp.1-13, 2017.
DOI : 10.1109/HPCA.2010.5416640

M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, Fault-tolerant method with distributed monitoring and management technique for 3D stacked meshes, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), pp.93-98, 2013.
DOI : 10.1109/CADS.2013.6714243

M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, MAFA: Adaptive faulttolerant routing algorithm for networks-on-chip, Proceedings -15th Euromicro Conference on Digital System Design, DSD 2012, pp.201-207, 2012.

M. Eggenberger and M. Radetzki, Scalable parallel simulation of networks on chip, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), pp.1-8, 2013.
DOI : 10.1109/NoCS.2013.6558402

M. Eggenberger, M. Strobel, and M. Radetzki, Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp.763-770, 2016.
DOI : 10.1109/PDP.2016.118

A. Eghbal, P. M. Yaghini, N. Bagherzadeh, and M. Khayambashi, Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip, IEEE Transactions on Computers, vol.64, issue.12, pp.3591-3604, 2015.
DOI : 10.1109/TC.2015.2401016

B. S. Feero and P. P. Pande, Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation, IEEE Transactions on Computers, vol.58, issue.1, pp.32-45, 2009.
DOI : 10.1109/TC.2008.142

E. Fleury and P. Fraigniaud, A general theory for deadlock avoidance in wormhole-routed networks, IEEE Transactions on Parallel and Distributed Systems, vol.9, issue.7, pp.626-638, 1998.
DOI : 10.1109/71.707539

URL : https://hal.archives-ouvertes.fr/inria-00098494

J. Flich and J. Duato, Logic-Based Distributed Routing for NoCs, IEEE Computer Architecture Letters, vol.7, issue.1, pp.13-16, 2008.
DOI : 10.1109/L-CA.2007.16

S. Foroutan, A. Sheibanyrad, and F. Petrot, Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.33, issue.8, pp.331208-1218, 2014.
DOI : 10.1109/TCAD.2014.2323219

URL : https://hal.archives-ouvertes.fr/hal-01195897

C. Glass and L. Ni, The Turn Model for Adaptive Routing, Proceedings the 19th Annual International Symposium on Computer Architecture, pp.278-287, 1992.

P. Gratz, B. Grot, and S. W. Keckler, Regional congestion awareness for load balance in networks-on-chip, 2008 IEEE 14th International Symposium on High Performance Computer Architecture, pp.203-214, 2008.
DOI : 10.1109/HPCA.2008.4658640

J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, A low latency router supporting adaptivity for on-chip interconnects, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.559-564, 2005.
DOI : 10.1145/1065579.1065726

J. Lee and K. Choi, A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), pp.0-1, 2013.
DOI : 10.1109/NoCS.2013.6558407

J. Lee, K. Kang, and K. Choi, REDELF, ACM Journal on Emerging Technologies in Computing Systems, vol.12, issue.3, pp.1-2622, 2015.
DOI : 10.1109/VLSI-SoC.2012.6378999

R. Mullins, Netmaker. [Online; accessed 03, p.108, 2009.

B. Niazmand, S. P. Azad, J. Flich, J. Raik, G. Jervan et al., Logic-based implementation of fault-tolerant routing in 3D network-on-chips, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp.1-8, 2016.
DOI : 10.1109/NOCS.2016.7579317

S. Pasricha and Y. Zou, A low overhead fault tolerant routing scheme for 3D networkson-chip, Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, pp.204-211, 2011.

V. F. Pavlidis and E. G. Friedman, 3-d topologies for networks-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1081-1090, 2007.

F. Pétrot, D. Hommais, and A. Greiner, Cycle precise core based hardware/software system simulation with predictable event propagation New Frontiers of Information Technology, EUROMICRO 97 Proceedings of the 23rd EUROMICRO Conference, pp.182-187, 1997.

T. Pinkston and S. Warnakulasuriya, Characterization of deadlocks in k-ary n-cube networks, IEEE Transactions on Parallel and Distributed Systems, vol.10, issue.9, pp.904-921, 1999.
DOI : 10.1109/71.798315

C. Pinto, S. Raghav, A. Marongiu, M. Ruggiero, D. Atienza et al., GPGPUaccelerated parallel and fast simulation of thousand-core platforms, Proceedings -11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, pp.53-62, 2011.

P. Ren, M. Lis, M. H. Cho, K. S. Shim, C. W. Fletcher et al., HORNET: A cycle-level multicore simulator, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, issue.6, pp.31890-903, 2012.

P. Ren, Q. Meng, X. Ren, and N. Zheng, Fault-tolerant Routing for On-chip Network Without Using Virtual Channels, Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, DAC '14, pp.1-6, 2014.
DOI : 10.1145/2593069.2593141

R. Salamat, M. Ebrahimi, and N. Bagherzadeh, An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip, 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp.392-395, 2015.
DOI : 10.1109/PDP.2015.91

R. Salamat, M. Ebrahimi, N. Bagherzadeh, and F. Verbeek, CoBRA: Low cost compensation of TSV failures in 3D-NoC, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.115-120, 2016.
DOI : 10.1109/DFT.2016.7684081

R. Salamat, M. Khayambashi, M. Ebrahimi, and N. Bagherzadeh, A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs, IEEE Transactions on Computers, vol.65, issue.11, p.79, 2016.
DOI : 10.1109/TC.2016.2532871

L. Schwiebert and D. Jayasimha, A universal proof technique for deadlock-free routing in interconnection networks, Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures , SPAA '95, pp.175-184, 1995.
DOI : 10.1145/215399.215440

L. Schwiebert and D. N. Jayasimha, Optimal fully adaptive wormhole routing for meshes, Proceedings of the 1993 ACM/IEEE conference on Supercomputing, pp.782-791, 1993.
DOI : 10.1145/169627.169835

URL : http://www.cs.wayne.edu/~loren/papers/sc93.pdf

S. Taktak, J. Desbarbieux, and E. Encrenaz, A tool for automatic detection of deadlock in wormhole networks on chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.13, issue.1, pp.6-14, 2008.
URL : https://hal.archives-ouvertes.fr/hal-01338483

F. Verbeek and J. Schmaltz, On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks, IEEE Transactions on Parallel and Distributed Systems, vol.22, issue.12, pp.2022-2032, 2011.
DOI : 10.1109/TPDS.2011.60

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards et al., On-Chip Interconnection Architecture of the Tile Processor, IEEE Micro, vol.27, issue.5, pp.15-31, 2007.
DOI : 10.1109/MM.2007.4378780

S. Xiao and W. C. Feng, Inter-block GPU communication via fast barrier synchronization, Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, pp.1-12, 2010.

H. Ying, K. Hofmann, and T. Hollstein, Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Networkon-Chips, 2014 International Conference on High Performance Computing & Simulation (HPCS), pp.516-522, 2014.

H. Ying, A. Jaiswal, T. Hollstein, and K. Hofmann, Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies, Journal of Systems Architecture, vol.59, issue.7, pp.59528-542, 2013.
DOI : 10.1016/j.sysarc.2013.03.005

M. Zolghadr, K. Mirhosseini, S. Gorgin, and A. Nayebi, GPU-based NoC simulator, Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011), pp.83-88, 2011.
DOI : 10.1109/MEMCOD.2011.5970514