Low-density parity-check codes, IEEE Transactions on Information Theory, vol.8, issue.1, 1963. ,
DOI : 10.1109/TIT.1962.1057683
Low-density parity-check codes based on nite geometries: a rediscovery and new results, IEEE Transactions on Information Theory, vol.47, issue.7, p.27112736, 2001. ,
A modied weighted bit-ipping decoding of low-density parity-check codes, IEEE Communications Letters, vol.8, issue.3, p.165167, 2004. ,
A improved bit-ipping decoding of lowdensity parity-check codes, IEEE Transactions on Information Theory, vol.51, issue.4, p.15941606, 2005. ,
An improvement on the modied weighted bit ipping decoding algorithm for ldpc codes, IEEE Communications Letters, vol.9, issue.9, p.814816, 2005. ,
Parallel weighted bit-ipping decoding, IEEE Communications Letters, vol.11, issue.8, p.671673, 2007. ,
DOI : 10.1109/lcomm.2007.070269
Improved parallel weighted bit-ipping decoding algorithm for ldpc codes, IET Communications, vol.3, issue.1, p.9199, 2009. ,
DOI : 10.1049/iet-com:20070632
Gradient descent bit ipping algorithms for decoding ldpc codes, IEEE Transactions on Communications, vol.58, issue.6, p.16101614, 2010. ,
DOI : 10.1109/isita.2008.4895387
URL : http://arxiv.org/pdf/0711.0261v2.pdf
Multi-bit ip type gradient descent bit ipping decoding using no thresholds, 2012 International Symposium on Information Theory and its Applications, p.610, 2012. ,
Improved gradient descent bit ipping algorithms for ldpc decoding, Digital Information and Communication Technology and it's Applications (DICTAP), 2012 Second International Conference on, p.324328, 2012. ,
Low Power Decoding of LDPC Codes, ISRN Sensor Networks, 2013. ,
DOI : 10.1109/JSSC.2005.864133
Weighted candidate bit based bit-ipping decoding algorithms for ldpc codes, 2013 3rd International Conference on Consumer Electronics, Communications and Networks, p.731734, 2013. ,
DOI : 10.1109/cecnet.2013.6703435
Two-bit bit ipping algorithms for ldpc codes and collective error correction, IEEE Transactions on Communications, vol.62, issue.4, p.11531163, 2014. ,
DOI : 10.1109/tcomm.2014.021614.130884
Noisy gradient descent bitip decoding for ldpc codes, IEEE Transactions on Communications, vol.62, issue.10, p.33853400, 2014. ,
DOI : 10.1109/tcomm.2014.2356458
URL : http://arxiv.org/pdf/1402.2773
Fault-tolerant probabilistic gradientdescent bit ipping decoder, IEEE Communications Letters, vol.18, issue.9, p.14871490, 2014. ,
DOI : 10.1109/lcomm.2014.2344031
Mixed modied weighted bit-ipping decoding of low-density parity-check codes, IET Communications, vol.9, issue.2, p.283290, 2015. ,
Multi-threshold bit ipping algorithm for decoding structured ldpc codes, IEEE Communications Letters, vol.19, issue.2, p.127130, 2015. ,
DOI : 10.1109/lcomm.2014.2373352
Dynamic weighted bit-ipping decoding algorithms for ldpc codes, IEEE Transactions on Communications, vol.63, issue.11, p.39503963, 2015. ,
DOI : 10.1109/tcomm.2015.2469780
URL : http://arxiv.org/pdf/1501.02428
An iterative bit ipping based decoding algorithm for ldpc codes, 2015 Iran Workshop on Communication and Information Theory (IWCIT), p.13, 2015. ,
DOI : 10.1109/iwcit.2015.7140214
Two-staged weighted bit ipping (wbf ) decoding algorithm for ldpc codes, 2015 IEEE 9th International Conference on Anti-counterfeiting, Security, and Identication (ASID), pp.141-144, 2015. ,
DOI : 10.1109/icasid.2015.7405679
Hybrid iterative decoding for ldpc codes based on gradient descent bit-ipping algorithm, 2016 8th International Conference on Wireless Communications Signal Processing (WCSP), p.13, 2016. ,
DOI : 10.1109/wcsp.2016.7752445
Multi-bit ipping decoding of ldpc codes for nand storage systems, IEEE Communications Letters, vol.PP, issue.99 11, 2017. ,
Finite Alphabet Iterative Decoders???Part II: Towards Guaranteed Error Correction of LDPC Codes via Iterative Decoder Diversity, IEEE Transactions on Communications, vol.61, issue.10, p.40464057, 2013. ,
DOI : 10.1109/TCOMM.2013.090513.120444
Flexible, cost-ecient, high-throughput architecture for layered ldpc decoders with fully-parallel processing units, 2016 Euromicro Conference on Digital System Design (DSD), p.230237, 2016. ,
DOI : 10.1109/dsd.2016.33
Low Complexity LDPC Code Decoders for Next Generation Standards, 2007 Design, Automation & Test in Europe Conference & Exhibition, p.16, 2007. ,
DOI : 10.1109/DATE.2007.364613
URL : http://cecs.uci.edu/~papers/date08/PAPERS/2007/DATE07/PDFFILES/03.2_1.PDF
Multi-gb/s ldpc code design and implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, p.262268, 2009. ,
Two reliabilitybased iterative majority-logic decoding algorithms for ldpc codes, IEEE Transactions on Communications, vol.57, issue.12, p.35973606, 2009. ,
DOI : 10.1109/tcomm.2009.12.080493
Ecient realization of probabilistic gradient descent bit ipping decoders, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), p.14941497, 2015. ,
A class of group-structured ldpc codes, Proc. 5th Int. Symp, 2001. ,
Design of capacityapproaching irregular low-density parity-check codes, IEEE Transactions on Information Theory, vol.47, issue.2, p.619637, 2001. ,
A dierential binary messagepassing ldpc decoder, IEEE Transactions on Communications, vol.57, issue.9, p.25182523, 2009. ,
DOI : 10.1109/glocom.2007.300
Highthroughput energy-ecient ldpc decoders using dierential binary message passing, IEEE Transactions on Signal Processing, vol.62, issue.3, p.619631, 2014. ,
DOI : 10.1109/tsp.2013.2293116
The Design and Analysis of Computer Algorithms, 1974. ,
Trapping set ontology, 47th Annual Allerton Conference on Communication, Control, and Computing (Allerton), p.17, 2009. ,
Approaching maximum likelihood decoding of nite length ldpc codes via faid diversity, 2012 IEEE Information Theory Workshop, p.487491, 2012. ,
Finite alphabet iterative decoding (faid) of the, 2010 6th International Symposium on Turbo Codes Iterative Information Processing, p.1115, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00520041
Approaching maximum likelihood performance of ldpc codes by stochastic resonance in noisy iterative decoders, Information Theory and Applications Workshop, 2016. ,
Error oors of ldpc codes, 41st Annual Allerton Conf on Communications Control and Computing, p.14261435, 2003. ,
FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL, 2012 International Conference on Communication Systems and Network Technologies, p.769773, 2012. ,
DOI : 10.1109/CSNT.2012.168
Fast and ecient circuit topologies fornding the maximum of n k-bit numbers, IEEE Transactions on Computers, vol.63, issue.8, p.18681881, 2014. ,
Fpga design of high throughput ldpc decoder based on imprecise oset min-sum decoding, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), p.14, 2015. ,
Noise-aided gradient descent bit-ipping decoders approaching maximum likelihood decoding, 2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), p.300304, 2016. ,
DOI : 10.1109/istc.2016.7593125