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Theses

3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond

Abstract : 3DVLSI integration, also known as monolithic or sequential integration is presented and evaluated in this thesis as a potential contender to continue the scaling for CMOS logic circuits. The main advantage of this technology compared to the already existing 3D parallel integration is its high alignment among tiers, enabling small size and pitch with the inter-tier contacts (3DCO). Another great 3DVLSI feature is its improved capability to place and route circuits, compared to the planar approach: the interconnections can be shorter as the design has an additional degree of freedom in the Z direction. For instance, long wires in planar circuits can cut thanks to 3DCO contacts, lowering the interconnection parasitic elements and speeding up the circuit as well as reducing the power. In this framework, the thesis has been divided into two parts: the first part is dedicated to the evaluation of Performance, Power and Area (PPA) of 3D circuits and gives design guidelines. The second part treats the variability in 3D circuits by using a 3D unified statistical model and propose an approach for the multi-tier variability.
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https://tel.archives-ouvertes.fr/tel-01726290
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Submitted on : Thursday, March 8, 2018 - 10:35:15 AM
Last modification on : Wednesday, October 14, 2020 - 4:20:03 AM
Long-term archiving on: : Saturday, June 9, 2018 - 1:52:54 PM

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  • HAL Id : tel-01726290, version 1

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Alexandre Ayres de Sousa. 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2017. English. ⟨NNT : 2017GREAT065⟩. ⟨tel-01726290⟩

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